Lines Matching full:_free
600 ? 9 A ` } ? ? ? ? ? ? + ? 5 ? ? ? ___error _free _close$UNIX2003 _cb_host_to_target_errno _isatty _lseek _cb_target_to_host_open _open$UNIX2003 ___memcpy_chk _read$UNIX2003 _xrealloc _write$UNIX2003 _fwrite$UNIX2003 _fflush _rename _system$UNIX2003 _time _unlink _stat$INODE64 ___memset_chk _fstat$INODE64 _lstat$INODE64 _ftruncate _truncate _vfprintf _vprintf _fputc _exit _default_callback _cb_read_target_syscall_maps _fopen$UNIX2003 _fclose _cb_target_to_host_syscall _cb_store_target_endian _cb_host_to_target_stat _strchr _atoi _strncmp _sim_cb_printf _sim_cb_eprintf _cb_init_open_map ___stdoutp _cb_init_syscall_map ___stderrp _cb_init_errno_map _wrap _fdbad _fdmap _os_close _os_get_errno _os_isatty _os_lseek _os_open _os_read ___inline_memcpy_chk _os_read_stdin _os_write _os_write_stdout _os_flush_stdout _os_write_stderr _os_flush_stderr _os_rename _os_system _os_time _os_unlink _os_stat _os_fstat ___inline_memset_chk _os_lstat _os_ftruncate _os_truncate _os_pipe _os_pipe_empty _os_pipe_nonempty _os_shutdown _os_init _os_printf_filtered _os_vprintf_filtered _os_evprintf_filtered _os_error
734 O ?? ?: $ ? ? ? ? ?? ?? ? z ?? ?? b B ? ?? ?? ? ? ? ?? ?? ? ? ? ? ? H * ? 4 % ? ? T ? v ? [ B ? _simulator_sysroot _xmalloc _strlen ___memmove_chk ___memcpy_chk _free _cb_syscall _abort _cb_target_to_host_syscall _cb_host_to_target_stat _xcalloc _cb_store_target_endian _cb_host_to_target_errno ___stack_chk_fail ___stack_chk_guard _get_string _get_path ___inline_memmove_chk ___inline_memcpy_chk
7056 ? ? ; U ? ? p e ? ? ? ? ? R 2 ? ? ? ' ? ! : b N ? _sim_io_error _mips_core_signal _trace_printf _map_to_str _sim_core_xor_read_buffer _sim_core_xor_write_buffer _sim_events_schedule _sim_io_poll_quit _free
10275 1 ? ? ? ? ? o ? ? = ? ( ? ? ? ? ? ? ? Z 6 ? ? ; U ? ? p D _ m ? ? ? ' ! : b - _sim_io_error _mips_core_signal _trace_printf _map_to_str _sim_core_xor_read_buffer _sim_core_xor_write_buffer _sim_events_schedule _sim_io_poll_quit _free _sim_elapsed_time_since _sim_core_read_buffer _abort _pr_addr _signal_exception _sim_io_eprintf _sim_engine_abort _idecode_issue _dotrace _trace_input_word2 _trace_result_word1 ___divdi3 ___moddi3 _trace_result_word2 ___udivdi3 ___umoddi3 _trace_input_word1 _semantic_SLLa_SPECIAL _semantic_MOVtf_SPECIAL _semantic_SRL_SPECIAL _semantic_SRA_SPECIAL _semantic_SLLV_SPECIAL _semantic_RSVD_SPECIAL _semantic_SRLV_SPECIAL _semantic_SRAV_SPECIAL _semantic_JR_SPECIAL _semantic_JALR_SPECIAL _semantic_MOVZ_SPECIAL _semantic_MOVN_SPECIAL _semantic_SYSCALL_SPECIAL _semantic_BREAK_SPECIAL _semantic_SYNC_SPECIAL _semantic_MFHI_SPECIAL _semantic_MTHI_SPECIAL _semantic_MFLO_SPECIAL _semantic_MTLO_SPECIAL _semantic_MULT_SPECIAL _semantic_MULTU_SPECIAL _semantic_DIV_SPECIAL _semantic_DIVU_SPECIAL _semantic_ADD_SPECIAL _semantic_ADDU_SPECIAL _semantic_SUB_SPECIAL _semantic_SUBU_SPECIAL _semantic_AND_SPECIAL _semantic_OR_SPECIAL _semantic_XOR_SPECIAL _semantic_NOR_SPECIAL _semantic_SLT_SPECIAL _semantic_SLTU_SPECIAL _semantic_TGE_SPECIAL _semantic_TGEU_SPECIAL _semantic_TLT_SPECIAL _semantic_TLTU_SPECIAL _semantic_TEQ_SPECIAL _semantic_TNE_SPECIAL _semantic_BLTZ_REGIMM _semantic_BGEZ_REGIMM _semantic_BLTZL_REGIMM _semantic_BGEZL_REGIMM _semantic_TGEI_REGIMM _semantic_TGEIU_REGIMM _semantic_TLTI_REGIMM _semantic_TLTIU_REGIMM _semantic_TEQI_REGIMM _semantic_TNEI_REGIMM _semantic_BLTZAL_REGIMM _semantic_BGEZAL_REGIMM _semantic_BLTZALL_REGIMM _semantic_BGEZALL_REGIMM _semantic_J_NORMAL _semantic_JAL_NORMAL _semantic_BEQ_NORMAL _semantic_BNE_NORMAL _semantic_BLEZ_NORMAL _semantic_BGTZ_NORMAL _semantic_ADDI_NORMAL _semantic_ADDIU_NORMAL _semantic_SLTI_NORMAL _semantic_SLTIU_NORMAL _semantic_ANDI_NORMAL _semantic_ORI_NORMAL _semantic_XORI_NORMAL _semantic_LUI_NORMAL _semantic_MFC0_COP0 _semantic_MTC0_COP0 _semantic_BC0F_COP0 _semantic_BC0T_COP0 _semantic_BC0FL_COP0 _semantic_BC0TL_COP0 _semantic_TLBR_COP0 _semantic_TLBWI_COP0 _semantic_TLBWR_COP0 _semantic_TLBP_COP0 _semantic_RFE_COP0 _semantic_ERET_COP0 _semantic_MFC1b_COP1 _semantic_CFC1b_COP1 _semantic_MTC1b_COP1 _semantic_CTC1b_COP1 _semantic_BC1b_COP1S _semantic_ADD_fmt_COP1 _semantic_SUB_fmt_COP1 _semantic_MUL_fmt_COP1 _semantic_DIV_fmt_COP1 _semantic_SQRT_fmt_COP1 _semantic_ABS_fmt_COP1 _semantic_MOV_fmt_COP1 _semantic_NEG_fmt_COP1 _semantic_ROUND_W_fmt_COP1 _semantic_TRUNC_W_COP1 _semantic_CEIL_W_COP1 _semantic_FLOOR_W_fmt_COP1 _semantic_MOVtf_fmt_COP1 _semantic_MOVZ_fmt_COP1 _semantic_MOVN_fmt_COP1 _semantic_RECIP_fmt_COP1 _semantic_RSQRT_fmt_COP1 _semantic_CVT_S_fmt_COP1 _semantic_CVT_D_fmt_COP1 _semantic_CVT_W_fmt_COP1 _semantic_C_cond_fmtb_COP1 _semantic_COPz_NORMAL _semantic_SWXC1_COP1X _semantic_BEQL_NORMAL _semantic_BNEL_NORMAL _semantic_BLEZL_NORMAL _semantic_BGTZL_NORMAL _semantic_LB_NORMAL _semantic_LH_NORMAL _semantic_LWL_NORMAL _semantic_LW_NORMAL _semantic_LBU_NORMAL _semantic_LHU_NORMAL _semantic_LWR_NORMAL _semantic_SB_NORMAL _semantic_SH_NORMAL _semantic_SWL_NORMAL _semantic_SW_NORMAL _semantic_SWR_NORMAL _semantic_CACHE_NORMAL _semantic_LL_NORMAL _semantic_LWC1_COP1 _semantic_LWCz_NORMAL _semantic_PREF_NORMAL _semantic_LDC1b_COP1 _semantic_SC_NORMAL _semantic_SWC1_COP1 _semantic_SWCz_NORMAL _semantic_SDC1b_COP1 _tracefh _DSPHI_REGNUM _sim_fpu_one _DSPLO_REGNUM _sim_fpu_qnan _sim_fpu_zero _current_target_byte_order _itable _LSMASKED _MSMASKED _LSEXTRACTED _MSEXTRACTED _LSINSERTED _MSINSERTED _LSSEXT _LSSEXT32 _MSSEXT _MSSEXT32 _LSMASKED8 _MSMASKED8 _LSEXTRACTED8 _MSEXTRACTED8 _LSINSERTED8 _MSINSERTED8 _ROT8 _ROTR8 _ROTL8 _LSSEXT8 _MSSEXT8 _LSMASKED16 _MSMASKED16 _LSEXTRACTED16 _MSEXTRACTED16 _LSINSERTED16 _MSINSERTED16 _ROT16 _ROTR16 _ROTL16 _LSSEXT16 _MSSEXT16 _LSMASKED32 _MSMASKED32 _LSEXTRACTED32 _MSEXTRACTED32 _LSINSERTED32 _MSINSERTED32 _ROT32 _ROTR32 _ROTL32 _LSMASKED64 _MSMASKED64 _LSEXTRACTED64 _MSEXTRACTED64 _LSINSERTED64 _MSINSERTED64 _ROT64 _ROTR64 _ROTL64 _LSSEXT64 _MSSEXT64 _endian_t2h_1 _endian_h2t_1 _swap_1 _endian_h2be_1 _endian_be2h_1 _endian_h2le_1 _endian_le2h_1 _offset_1 _endian_t2h_2 _endian_h2t_2 _swap_2 _endian_h2be_2 _endian_be2h_2 _endian_h2le_2 _endian_le2h_2 _offset_2 _endian_t2h_4 _endian_h2t_4 _swap_4 _endian_h2be_4 _endian_be2h_4 _endian_h2le_4 _endian_le2h_4 _offset_4 _endian_t2h_8 _endian_h2t_8 _swap_8 _endian_h2be_8 _endian_be2h_8 _endian_h2le_8 _endian_le2h_8 _offset_8 _endian_t2h_16 _endian_h2t_16 _swap_16 _endian_h2be_16 _endian_be2h_16 _endian_h2le_16 _endian_le2h_16 _offset_16 _sim_endian_split_16 _sim_endian_join_16 _sim_core_find_mapping _sim_core_translate _sim_core_trace_16 _sim_core_read_aligned_16 _sim_core_read_unaligned_16 _sim_core_write_aligned_16 _sim_core_write_unaligned_16 _sim_core_trace_8 _sim_core_read_aligned_8 _sim_core_read_unaligned_8 _sim_core_write_aligned_8 _sim_core_write_unaligned_8 _sim_core_read_misaligned_7 _sim_core_write_misaligned_7 _sim_core_read_misaligned_6 _sim_core_write_misaligned_6 _sim_core_read_misaligned_5 _sim_core_write_misaligned_5 _sim_core_trace_4 _sim_core_read_aligned_4 _sim_core_read_unaligned_4 _sim_core_write_aligned_4 _sim_core_write_unaligned_4 _sim_core_read_misaligned_3 _sim_core_write_misaligned_3 _sim_core_trace_2 _sim_core_read_aligned_2 _sim_core_read_unaligned_2 _sim_core_write_aligned_2 _sim_core_write_unaligned_2 _sim_core_trace_1 _sim_core_read_aligned_1 _sim_core_write_aligned_1 _sim_events_poll _sim_events_free _sim_events_time _sim_events_elapsed_time _sim_events_remain_time _update_time_from_event _sim_watch_valid _sim_events_tick _sim_events_tickn _sim_events_slip _sim_events_preprocess _sim_events_process _print_bits _pack_fpu _unpack_fpu _fpu2i _sim_fpu_is_zero _sim_fpu_is_snan _sim_fpu_is_qnan _sim_fpu_is_infinity _i2fpu _fpu2u _sim_fpu_is_nan _u2fpu _sim_fpu_32to _sim_fpu_232to _sim_fpu_64to _sim_fpu_to32 _sim_fpu_to232 _sim_fpu_to64 _sim_fpu_fractionto _sim_fpu_tofraction _do_normal_overflow _do_normal_underflow _do_normal_round _do_round _sim_fpu_round_32 _sim_fpu_round_64 _sim_fpu_add _sim_fpu_sub _sim_fpu_mul _sim_fpu_div _sim_fpu_max _sim_fpu_min _sim_fpu_neg _sim_fpu_abs _sim_fpu_inv _sim_fpu_sqrt _sim_fpu_i32to _sim_fpu_u32to _sim_fpu_i64to _sim_fpu_u64to _sim_fpu_to32i _sim_fpu_to32u _sim_fpu_to64i _sim_fpu_to64u _sim_fpu_2d _sim_fpu_d2 _sim_fpu_is_number _sim_fpu_is_denorm _sim_fpu_sign _sim_fpu_exp _sim_fpu_fraction _sim_fpu_guard _sim_fpu_is _sim_fpu_cmp _sim_fpu_is_lt _sim_fpu_lt _sim_fpu_is_le _sim_fpu_le _sim_fpu_is_eq _sim_fpu_eq _sim_fpu_is_ne _sim_fpu_ne _sim_fpu_is_ge _sim_fpu_ge _sim_fpu_is_gt _sim_fpu_gt _sim_fpu_print_fpu _sim_fpu_printn_fpu _sim_fpu_print_status _address_translation _prefetch _load_memory _store_memory _ifetch32 _ifetch16 _sync_operation _dcache_warning.16486 _icache_warning.16485 _cache_op _pending_tick _semantic_illegal _delayslot32 _nullify_next_insn32 _loadstore_ea _not_word_value _unpredictable _check_mf_cycles _check_mt_hilo _check_mf_hilo _check_mult_hilo _check_div_hilo _check_u64 _do_addiu _do_addu _do_and _do_daddiu _do_daddu _do_ddiv _do_ddivu _do_div _do_divu _do_dmultx _do_dmult _do_dmultu _do_dror _do_dsll _do_dsllv _do_dsra _do_dsrav _do_dsrl _do_dsrlv _do_dsubu _do_load _do_load_left _do_load_right _do_mfhi _do_mflo _do_mult _do_multu _do_nor _do_or _do_ori _do_ror _do_store _do_store_left _do_store_right _do_sll _do_sllv _do_slt _do_slti _do_sltiu _do_sltu _do_sra _do_srav _do_srl _do_srlv _do_subu _do_xor _do_xori _str_FMT _str_TF _str_ND _str_COND _check_fmt_p _check_fpu _delayslot16 _basepc _do_save _str_MFHI _str_SAT _str_UNS _do_vr_mul_op _do_ph_op _do_w_op _do_qb_op _do_qb_shift _do_ph_shift _do_w_shll _do_w_shra _do_qb_muleu _do_ph_muleq _do_qb_dot_product _do_ph_dot_product _do_w_dot_product _do_ph_maq _do_qb_cmpu _do_qb_cmpgu _do_ph_cmpu _do_w_extr _do_h_extr _do_extp _do_shilo _sim_core_dummy_16 _sim_core_dummy_8 _sim_core_dummy_4 _sim_core_dummy_2 #1/12 1334569271 59446 0 100644 164 `
13197 ? $ ? $ ? n I K ? 4 ? ? ? ( Q = ? ? ? ? ? { ? ? I 4 ? ? ? ? ? ? f B ? ? ; U ? ? p P k y ? ? ? ' ! : b 9 _sim_io_error _mips_core_signal _trace_printf _map_to_str _sim_core_xor_read_buffer _sim_core_xor_write_buffer _sim_events_schedule _sim_io_poll_quit _free
13264 ? g W u q ? ? ? x ? ? ? ? ? ? < 6 P x 3 + _sim_addr_range_hit_p _free ___memset_chk _zalloc _xmalloc _sim_addr_range_add _sim_addr_range_delete _insert_range _delete_range _frob_range ___inline_memset_chk _free_search_tree _build_tree_1 _build_search_tree
14452 ? ?$ ? ?9 ? : ? W: ? ?: ? ?; ? ?; ? ?; < ?< " f; 1 y; @ ?; G X ? ^ Y u ? ( ? ? ? ? 6 s V W M ? * ; ? ? ? ? ? ? ? l ? ? ? N ? ? ? ? ? @ X r # @ ? ? _sim_io_error _sim_events_install _sim_module_add_uninstall_fn _sim_module_add_init_fn _sim_module_add_resume_fn _sim_module_add_suspend_fn _sim_elapsed_time_get _sim_elapsed_time_since ___memset_chk _zalloc _sim_events_schedule _sim_io_poll_quit _free _sim_events_time _sim_events_elapsed_time _sim_events_remain_time _trace_printf _memset _sim_events_schedule_vtracef _sim_events_schedule_tracef _vasprintf _sim_events_schedule_after_signal _sim_engine_abort _sim_events_watch_clock _sim_events_watch_sim _sim_events_watch_core _sim_events_deschedule _sim_events_tick _sim_events_tickn _sim_events_slip _sim_events_preprocess _sim_events_process _sim_core_read_buffer _current_target_byte_order _next_event_queue _sim_events_uninstall _sim_events_init _sim_events_resume _sim_events_suspend _sim_events_zalloc ___inline_memset_chk _sim_events_free _sim_events_poll _insert_sim_event _update_time_from_event _sim_watch_valid _endian_t2h_1 _endian_t2h_2 _endian_t2h_4 _endian_t2h_8 _endian_be2h_1 _endian_be2h_2 _endian_be2h_4 _endian_be2h_8 _endian_le2h_1 _endian_le2h_2 _endian_le2h_4 _endian_le2h_8
15401 < - ?S ? ' ? ?0 ? ? ?* ? ? ?& ? ? p ? ? S ? ? ? ?? ? ? ? ? | m ?? ? U M ? ? ? ? ? ? ? ? ? ? 6 H * a { Y S _sim_load_file _bfd_openr _bfd_get_error _bfd_errmsg _bfd_check_format _bfd_close _time _malloc _bfd_get_section_contents _free _bfd_cache_close _eprintf _xprintf _xprintf_bfd_vma _report_transfer_performance
16156 ?? ?L ? ? , r , \ , @ , % , 9 ? ?8# ?? ? ?8# ?? ? ' ? ?8# ?? : ?8# ?? ? ?8# ?? ? ?8# ?? ? * ? ?8# ?? ? i ?? ?? c # T ?i ?? ; ?D ?? ?? ?? ? ?(# ?v ? + ? ? ?(# ?v ? ?(# ?v ? r 2 + " $ ?? ?v ? $ ? ?? ?v ? $ ? ?? ?v ? ? ? " { ?? ?v d T ! = " . ?d ?v # " ?0 ?v " ? ? ?v ? " ? ?? ?v ? " ? ?? ?v ? ' ? ?? ?v ? ?0# ?v { ' l ?? ?v b ' S ?? ?v A " 2 ?\ ?v " ? ?v ? " ? ?4 ?v ? ' ? ?( ?v ? ' ? ? ?v ' p ? ?v ^ " O ?? ?v 5 ?4# ?v + ' ?? ?v ?4# ?v ? ' ? ?? ?v ? ?? ?v ? ?U ?v ? ?F ?v ? ?d ?v ? ?? ?v ? ?? ?v ? ?? ?v ? ?Q ?v ? ?n ?v ? ?? ?v ? ?+ ?v ? ?] ?v ? ?F ?v ? ?, ?v ? ? ?v ? ?? ?v * ? ? ? ? ? ? ? ? ? ? ? ? ? ? h ` \ D < 8 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? l d ` \ H @ < 8 $ % ? ? ? j ? 8# ? + ? 7 ? @ ? J X S T + ? ? ? ? n ? ? ? ? f ? W H = ? ? ? ? | H ? r j Z 8 ( ? m z R " ? ? _sim_add_option_table _xmalloc _strcmp _sim_io_eprintf _sim_do_command _bfd_scan_arch _bfd_arch_list _abort _sim_io_printf _free _xstrdup _sim_print_help _exit _standard_install _sim_io_error ___memset_chk _sim_parse_args _zalloc _asprintf _getopt_long _dupargv _zfree _strlen ___maskrune _strncmp _sim_args_command _buildargv _freeargv _strchr _sim_cpu_lookup _optind _optarg _simulator_sysroot __DefaultRuneLocale _current_alignment _current_target_byte_order _standard_options _standard_option_handler _arg_table.11933 _dup_arg_p ___inline_memset_chk _print_help _isspace ___istype _isascii _find_match #1/20 1334569267 59446 0 100644 18468 `
17062 ' ? ? ? N ? l ? _zalloc _xmalloc ___memset_chk _zfree _free _sim_state_alloc _sim_state_free _sim_io_error _sim_cpu_lookup _strcmp _sim_cpu_msg_prefix _sim_io_eprintf_cpu _sim_io_eprintf _sim_io_evprintf _sim_add_commas _sim_analyze_program _bfd_openr _bfd_get_error _bfd_errmsg _bfd_check_format _bfd_close _bfd_set_arch_info _bfd_get_arch _bfd_get_arch_info _bfd_cache_close _sim_elapsed_time_get _getrusage _sim_elapsed_time_since _sim_do_commandf _vasprintf _sim_do_command _map_to_str ___sprintf_chk _access_to_str _transfer_to_str _current_state ___inline_memset_chk _str.11785 _str.11809 #1/20 1334569268 59446 0 100644 8276 `
