| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.h | 83 /// BasePtr - ARM physical register used as a base ptr in complex stack
86 unsigned BasePtr;
151 unsigned getBaseRegister() const { return BasePtr; }
|
| Thumb1FrameLowering.cpp | 61 unsigned BasePtr = RegInfo->getBaseRegister();
167 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
|
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| LoopIdiomRecognize.cpp | 483 Value *BasePtr =
488 if (mayLoopAccessLocation(BasePtr, AliasAnalysis::ModRef,
493 deleteIfDeadInstruction(BasePtr, *SE);
515 NewCall = Builder.CreateMemSet(BasePtr, SplatValue,NumBytes,StoreAlignment);
532 NewCall = Builder.CreateCall3(MSP, BasePtr, PatternPtr, NumBytes);
|
| /external/clang/lib/CodeGen/ |
| CGClass.cpp | 627 llvm::Type *BasePtr = ConvertType(BaseElementTy);
628 BasePtr = llvm::PointerType::getUnqual(BasePtr);
630 BasePtr);
[all...] |
| /external/llvm/lib/Bitcode/Reader/ |
| BitcodeReader.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 415 SDValue BasePtr = LD->getBasePtr();
421 IsWordAlignedBasePlusConstantOffset(BasePtr, Base, Offset)) {
426 return DAG.getLoad(getPointerTy(), DL, Chain, BasePtr,
461 BasePtr, LD->getPointerInfo(), MVT::i16,
463 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
479 // Lower to a call to __misaligned_load(BasePtr).
485 Entry.Node = BasePtr;
517 SDValue BasePtr = ST->getBasePtr();
525 SDValue StoreLow = DAG.getTruncStore(Chain, dl, Low, BasePtr,
529 SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr,
[all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_2_7/ |
| BitcodeReader.cpp | [all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_3_0/ |
| BitcodeReader.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorTypes.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
