| /external/clang/test/CodeGenCXX/ |
| debug-info-byval.cpp | 4 class DAG {
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.h | 27 const ScheduleDAG *DAG;
31 ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_) {}
|
| PPCISelLowering.cpp | 1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
411 // We have target-specific dag combine patterns for the following nodes:
705 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
748 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
751 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
755 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
758 return DAG.getTargetConstant(Val, MVT::i32);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ScoreboardHazardRecognizer.h | 96 const ScheduleDAG *DAG;
109 const ScheduleDAG *DAG,
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.h | 34 /// the DAG and must be handled explicitly by schedulers.
39 SelectionDAG *DAG; // DAG of the current basic block
51 void Run(SelectionDAG *dag, MachineBasicBlock *bb);
81 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
|
| LegalizeTypes.h | 1 //===-- LegalizeTypes.h - Definition of the DAG Type Legalizer class ------===//
37 SelectionDAG &DAG;
68 return TLI.getTypeAction(*DAG.getContext(), VT);
73 return TLI.getTypeAction(*DAG.getContext(), VT) == TargetLowering::TypeLegal;
119 explicit DAGTypeLegalizer(SelectionDAG &dag)
120 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
127 /// top-down traversal of the dag, legalizing types as it goes. Returns
201 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op
[all...] |
| LegalizeVectorOps.cpp | 36 SelectionDAG& DAG;
77 VectorLegalizer(SelectionDAG& dag) :
78 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
88 DAG.AssignTopologicalOrder();
89 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
90 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
94 SDValue OldRoot = DAG.getRoot();
96 DAG.setRoot(LegalizedNodes[OldRoot])
[all...] |
| SelectionDAGBuilder.h | 1 //===-- SelectionDAGBuilder.h - Selection-DAG building --------------------===//
83 /// CurDebugLoc - current file + line number. Changes as we build the DAG.
294 SelectionDAG &DAG;
329 /// no subsequent DAG nodes should be created.
335 SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
337 : SDNodeOrder(0), TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
338 DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
339 HasTailCall(false), Context(dag.getContext())
[all...] |
| LegalizeDAG.cpp | 52 SelectionDAG &DAG;
63 explicit SelectionDAGLegalize(SelectionDAG &DAG);
153 DAG.RemoveDeadNode(N, this);
159 DAG.ReplaceAllUsesWith(Old, New, this);
163 DAG.ReplaceAllUsesWith(Old, New, this);
167 DAG.ReplaceAllUsesWith(Old, New, this);
188 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
202 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
205 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
206 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo())
[all...] |
| TargetLowering.cpp | [all...] |
| DAGCombiner.cpp | 1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
40 STATISTIC(NodesCombined , "Number of dag nodes combined");
58 SelectionDAG &DAG;
85 // AA - Used for DAG load/store alias analysis.
162 /// target-specific DAG combines.
165 // Visitation implementation - Implement dag node combining for different
301 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes)
[all...] |
| SelectionDAGBuilder.cpp | 1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
72 // Limit the width of DAG chains. This is important in general to prevent
73 // prevent DAG-based analysis from blowing up. For example, alias analysis and
76 // future analyses are likely to have the same behavior. Limiting DAG width is
88 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
97 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
105 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2)
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineScheduler.cpp | 129 /// consistent with the DAG builder, which traverses the interior of the
132 /// This design avoids exposing scheduling boundaries to the DAG builder,
133 /// simplifying the DAG builder's support for "special" target instructions.
173 // boundary at the bottom of the region. The DAG does not include RegionEnd,
255 /// Initialize the strategy after building the DAG for a new region.
256 virtual void initialize(ScheduleDAGMI *DAG) = 0;
412 // Release all DAG roots for scheduling.
470 ScheduleDAGMI *DAG;
476 virtual void initialize(ScheduleDAGMI *dag) {
477 DAG = dag
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 590 /// hasTargetDAGCombine - If true, the target has custom DAG combine
737 /// getInsertFencesFor - return whether the DAG builder should automatically
750 SelectionDAG &/*DAG*/) const {
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===//
159 // We have target-specific dag combine patterns for the following nodes:
167 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
170 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
171 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
172 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
173 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
174 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
175 case ISD::LOAD: return LowerLOAD(Op, DAG);
176 case ISD::STORE: return LowerSTORE(Op, DAG);
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 252 throw TGError(TheDef->getLoc(), "Invalid dag '" +
508 // SubRegClasses is a list<dag> containing (RC, subregindex, ...) dags.
511 DagInit *DAG = dynamic_cast<DagInit*>(*i);
512 if (!DAG) throw "SubRegClasses must contain DAGs";
513 DefInit *DAGOp = dynamic_cast<DefInit*>(DAG->getOperator());
516 throw "Operator '" + DAG->getOperator()->getAsString() +
519 for (DagInit::const_arg_iterator ai = DAG->arg_begin(), ae = DAG->arg_end();
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 1 //===-- SPUISelLowering.cpp - Cell SPU DAG Lowering Implementation --------===//
48 //! Expand a library call into an actual call DAG node
56 ExpandLibCall(RTLIB::Libcall LC, SDValue Op, SelectionDAG &DAG,
61 SDValue InChain = DAG.getEntryNode();
67 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
74 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
79 Op.getNode()->getValueType(0).getTypeForEVT(*DAG.getContext());
85 Callee, Args, DAG, Op.getDebugLoc());
464 // We have target-specific dag combine patterns for the following nodes:
558 LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
11 // selection DAG.
51 static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) {
52 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
53 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
444 static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG,
451 SelectMadd(N, &DAG))
457 static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG,
464 SelectMsub(N, &DAG))
470 static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG,
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
11 // selection DAG.
485 // In another words, find a way when "copysign" appears in DAG with vector
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
11 // selection DAG.
58 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
61 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
68 SelectionDAG &DAG,
74 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
79 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
93 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
94 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
103 /// Generate a DAG to put 128-bits into a vector > 128 bits. Thi
[all...] |
| /prebuilts/tools/common/eclipse/ |
| org.eclipse.ui.workbench.texteditor_3.6.1.r361_v20100714-0800.jar | |
