| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 120 // DstReg = LDriw_pred [R30], ofst.
121 int DstReg = MI->getOperand(0).getReg();
122 assert(Hexagon::PredRegsRegClass.contains(DstReg) &&
143 DstReg).addReg(HEXAGON_RESERVED_REG_2);
152 DstReg).addReg(HEXAGON_RESERVED_REG_2);
158 DstReg).addReg(HEXAGON_RESERVED_REG_2);
|
| HexagonPeephole.cpp | 131 unsigned DstReg = Dst.getReg();
134 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
139 PeepholeMap[DstReg] = SrcReg;
149 unsigned DstReg = Dst.getReg();
152 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
157 PeepholeMap[DstReg] = SrcReg;
172 unsigned DstReg = Dst.getReg();
174 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
|
| /external/llvm/lib/CodeGen/ |
| RegisterCoalescer.h | 32 /// DstReg - The register that will be left after coalescing. It can be a
34 unsigned DstReg;
36 /// SrcReg - the virtual register that will be coalesced into dstReg.
39 /// subReg_ - The subregister index of srcReg in DstReg. It is possible the
40 /// coalesce SrcReg into a subreg of the larger DstReg when DstReg is a
50 /// Flipped - True when DstReg and SrcReg are reversed from the original
54 /// NewRC - The register class of the coalesced register, or NULL if DstReg
60 : TII(tii), TRI(tri), DstReg(0), SrcReg(0), SubIdx(0),
67 /// flip - Swap SrcReg and DstReg. Return false if swapping is impossibl
[all...] |
| ExpandPostRAPseudos.cpp | 53 void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
65 /// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead,
69 ExpandPostRA::TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
73 if (MII->addRegisterDead(DstReg, TRI))
103 unsigned DstReg = MI->getOperand(0).getReg();
109 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
111 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
123 if (DstReg != InsReg) {
|
| OptimizePHIs.cpp | 87 unsigned DstReg = MI->getOperand(0).getReg();
100 if (SrcReg == DstReg)
130 unsigned DstReg = MI->getOperand(0).getReg();
131 assert(TargetRegisterInfo::isVirtualRegister(DstReg) &&
142 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DstReg),
|
| MachineSink.cpp | 120 unsigned DstReg = MI->getOperand(0).getReg();
122 !TargetRegisterInfo::isVirtualRegister(DstReg) ||
127 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg);
136 MRI->replaceRegWith(DstReg, SrcReg);
|
| PeepholeOptimizer.cpp | 131 unsigned SrcReg, DstReg, SubIdx;
132 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
135 if (TargetRegisterInfo::isPhysicalRegister(DstReg) ||
147 UI = MRI->use_nodbg_begin(DstReg);
226 UI = MRI->use_nodbg_begin(DstReg);
240 // About to add uses of DstReg, clear DstReg's kill flags.
242 MRI->clearKillFlags(DstReg);
247 .addReg(DstReg, 0, SubIdx);
|
| LiveDebugVariables.cpp | 566 unsigned DstReg = MI->getOperand(0).getReg();
572 if (!TargetRegisterInfo::isVirtualRegister(DstReg))
582 if (!LIS.hasInterval(DstReg))
584 LiveInterval *DstLI = &LIS.getInterval(DstReg);
[all...] |
| TwoAddressInstructionPass.cpp | 147 void ScanUses(unsigned DstReg, MachineBasicBlock *MBB,
153 void CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs, unsigned DstReg);
409 unsigned &SrcReg, unsigned &DstReg,
412 DstReg = 0;
414 DstReg = MI.getOperand(0).getReg();
417 DstReg = MI.getOperand(0).getReg();
423 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
458 unsigned SrcReg, DstReg;
461 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
469 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
[all...] |
| RegisterCoalescer.cpp | 113 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
147 unsigned DstReg, MachineInstr *CopyMI);
155 unsigned DstReg,
160 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
161 /// update the subregister number if it is not zero. If DstReg is a
236 SrcReg = DstReg = SubIdx = 0;
314 DstReg = Dst;
320 if (SubIdx || TargetRegisterInfo::isPhysicalRegister(DstReg))
322 std::swap(SrcReg, DstReg);
342 // Now check that Dst matches DstReg
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsExpandPseudo.cpp | 94 unsigned DstReg = I->getOperand(0).getReg();
99 TM.getRegisterInfo()->getSubRegisters(DstReg);
109 unsigned DstReg = I->getOperand(0).getReg();
116 BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(*(SubReg + N));
|
| MipsISelDAGToDAG.cpp | 190 unsigned DstReg = 0, ZeroReg = 0;
196 DstReg = MI.getOperand(0).getReg();
201 DstReg = MI.getOperand(0).getReg();
205 if (!DstReg)
209 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
|
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.cpp | 207 unsigned DstReg = MI.getOperand(0).getReg();
209 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
210 .addReg(DstReg).addImm(-Offset);
212 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
213 .addReg(DstReg).addImm(Offset);
|
| MSP430ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 209 unsigned DstReg = MI->getOperand(0).getReg();
233 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead));
|
| Thumb2ITBlockPass.cpp | 121 unsigned DstReg = MI->getOperand(0).getReg();
125 if (Uses.count(DstReg) || Defs.count(SrcReg))
|
| ARMExpandPseudoInsts.cpp | 388 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
390 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
428 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
515 unsigned DstReg = 0;
519 DstReg = MI.getOperand(OpIdx++).getReg();
520 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
569 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
616 unsigned DstReg = MI.getOperand(0).getReg();
625 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
627 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)
[all...] |
| ARMAsmPrinter.cpp | [all...] |
| ARMFastISel.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 132 unsigned DstReg = MI->getOperand(0).getReg();
135 if (DstReg != SrcReg)
136 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
140 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
144 if (DstReg != SrcReg)
145 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
149 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
153 if (DstReg != SrcReg)
154 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
158 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 798 unsigned DstReg = VA.getLocReg();
801 if (!SrcRC->contains(DstReg))
804 DstReg).addReg(SrcReg);
[all...] |
| X86InstrInfo.cpp | [all...] |
