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    Searched defs:Orders (Results 1 - 3 of 3) sorted by null

  /external/llvm/utils/TableGen/
CodeGenRegisters.h 166 // Allocation orders. Order[0] always contains all registers in Members.
167 std::vector<SmallVector<Record*, 16> > Orders;
272 return Orders[No];
275 // Return the total number of allocation orders available.
276 unsigned getNumOrders() const { return Orders.size(); }
  /external/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGSDNodes.cpp 668 SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,
686 Orders.push_back(std::make_pair(DVOrder, DbgMI));
700 SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,
706 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0);
713 Orders.push_back(std::make_pair(Order, (MachineInstr*)0));
717 Orders.push_back(std::make_pair(Order, prior(Emitter.getInsertPos())));
718 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order);
766 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders;
807 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen);
814 ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders,
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  /external/clang/lib/CodeGen/
CGBuiltin.cpp     [all...]

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