| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 60 unsigned PredReg = 0;
61 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg);
108 unsigned PredReg = 0;
109 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
180 ARMCC::CondCodes Pred, unsigned PredReg,
195 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
202 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
211 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
217 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
403 unsigned PredReg;
[all...] |
| MLxExpansionPass.cpp | 219 unsigned PredReg = MI->getOperand(++NextOp).getReg();
230 MIB.addImm(Pred).addReg(PredReg);
242 MIB.addImm(Pred).addReg(PredReg);
|
| Thumb2ITBlockPass.cpp | 173 unsigned PredReg = 0;
174 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
|
| ARMBaseRegisterInfo.cpp | 695 unsigned PredReg, unsigned MIFlags) const {
705 .addImm(0).addImm(Pred).addReg(PredReg)
729 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
732 Pred, PredReg, TII);
735 Pred, PredReg, TII);
768 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
769 unsigned PredReg = Old->getOperand(2).getReg();
770 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
772 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
773 unsigned PredReg = Old->getOperand(3).getReg()
[all...] |
| ARMExpandPseudoInsts.cpp | 614 unsigned PredReg = 0;
615 ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg);
638 LO16.addImm(Pred).addReg(PredReg).addReg(0);
639 HI16.addImm(Pred).addReg(PredReg).addReg(0);
[all...] |
| Thumb2SizeReduction.cpp | 543 unsigned PredReg = 0;
544 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) {
642 unsigned PredReg = 0;
643 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
734 unsigned PredReg = 0;
735 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
[all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMLoadStoreOptimizer.cpp | 95 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
109 unsigned PredReg,
115 ARMCC::CondCodes Pred, unsigned PredReg,
286 unsigned PredReg, unsigned Scratch, DebugLoc dl,
340 .addImm(Pred).addReg(PredReg).addReg(0);
351 .addImm(Pred).addReg(PredReg);
371 ARMCC::CondCodes Pred, unsigned PredReg,
416 Pred, PredReg, Scratch, dl, Regs, ImpDefs))
448 ARMCC::CondCodes Pred, unsigned PredReg,
501 Base, false, Opcode, Pred, PredReg, Scratch, dl, Merges)
[all...] |
