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    Searched defs:Registers (Results 1 - 9 of 9) sorted by null

  /external/v8/src/mips/
constants-mips.h 83 // Registers and FPURegisters.
85 // Number of general purpose registers.
89 // Number of registers with HI, LO, and pc.
95 // Number coprocessor registers.
99 // FPU (coprocessor 1) control registers. Currently only FCSR is implemented.
127 class Registers {
183 // the simulator will run through them and print the registers.
566 // registers and other constants.
  /external/llvm/utils/TableGen/
RegisterInfoEmitter.cpp 31 // runEnums - Print out enum values for all of the registers.
34 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
37 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
39 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
56 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
57 OS << " " << Registers[i]->getName() << " = " <<
58 Registers[i]->EnumValue << ",\n";
59 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &
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AsmWriterEmitter.cpp 481 const std::vector<CodeGenRegister*> &Registers) {
483 SmallVector<std::string, 4> AsmNames(Registers.size());
484 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
485 const CodeGenRegister &Reg = *Registers[i];
524 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
537 const std::vector<CodeGenRegister*> &Registers =
551 O << " assert(RegNo && RegNo < " << (Registers.size()+1)
557 emitRegisterNameString(O, AltNameIndices[i]->getName(), Registers);
559 emitRegisterNameString(O, "", Registers);
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CodeGenRegisters.h 103 // Get a map of sub-registers computed lazily.
104 // This includes unique entries for all sub-sub-registers.
108 assert(SubRegsComplete && "Must precompute sub-registers");
112 // Add sub-registers to OSet following a pre-order defined by the .td file.
116 // List of super-registers in topological order, small to large.
119 // Get the list of super-registers. This is valid after getSubReg
120 // visits all registers during RegBank construction.
122 assert(SubRegsComplete && "Must precompute sub-registers");
166 // Allocation orders. Order[0] always contains all registers in Members.
181 // registers have a SubRegIndex sub-register
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AsmMatcherEmitter.cpp 177 /// For register classes, the records for all the registers in this class.
178 std::set<Record*> Registers;
198 // Registers classes are only related to registers classes, and only if
206 std::set_intersection(Registers.begin(), Registers.end(),
207 RHS.Registers.begin(), RHS.Registers.end(),
669 // Collect singleton registers, if used.
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CodeGenRegisters.cpp 94 // Iterate over all register units in a set of registers.
204 // Add this as a super-register of SR now all sub-registers are in the list.
206 // order getSubRegs is called on all registers.
319 // registers using a worklist.
331 assert(SubRegsComplete && "Must precompute sub-registers");
355 // A RegisterTuples def is used to generate pseudo-registers from lists of
356 // sub-registers. We provide a SetTheory expander class that returns the new
357 // registers.
367 throw TGError(Def->getLoc(), "Tuples must have at least 2 sub-registers");
432 // Composite registers are always covered by sub-registers
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  /external/grub/netboot/
3c90x.c 54 enum Registers
83 /** following are windowed registers **/
771 /** Program the MAC address into the station address registers **/
  /external/v8/src/arm/
constants-arm.h 94 // Number of registers in normal ARM mode.
441 // These constants are declared in assembler-arm.cc, as they use named registers
738 class Registers {
  /external/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp 49 // Map of register aliases registers via the .req directive.
305 SmallVector<unsigned, 8> Registers;
345 // A vector register list is a sequential list of 1 to 4 registers.
429 Registers = o.Registers;
512 return Registers;
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