1 //===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the LiveInterval analysis pass. Given some numbering of 11 // each the machine instructions (in this implemention depth-first order) an 12 // interval [i, j) is said to be a live interval for register v if there is no 13 // instruction with number j' > j such that v is live at j' and there is no 14 // instruction with number i' < i such that v is live at i'. In this 15 // implementation intervals can have holes, i.e. an interval might look like 16 // [1,20), [50,65), [1000,1001). 17 // 18 //===----------------------------------------------------------------------===// 19 20 #ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H 21 #define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H 22 23 #include "llvm/CodeGen/MachineBasicBlock.h" 24 #include "llvm/CodeGen/MachineFunctionPass.h" 25 #include "llvm/CodeGen/LiveInterval.h" 26 #include "llvm/CodeGen/SlotIndexes.h" 27 #include "llvm/ADT/BitVector.h" 28 #include "llvm/ADT/DenseMap.h" 29 #include "llvm/ADT/SmallPtrSet.h" 30 #include "llvm/ADT/SmallVector.h" 31 #include "llvm/Support/Allocator.h" 32 #include <cmath> 33 #include <iterator> 34 35 namespace llvm { 36 37 class AliasAnalysis; 38 class LiveVariables; 39 class MachineLoopInfo; 40 class TargetRegisterInfo; 41 class MachineRegisterInfo; 42 class TargetInstrInfo; 43 class TargetRegisterClass; 44 class VirtRegMap; 45 46 class LiveIntervals : public MachineFunctionPass { 47 MachineFunction* mf_; 48 MachineRegisterInfo* mri_; 49 const TargetMachine* tm_; 50 const TargetRegisterInfo* tri_; 51 const TargetInstrInfo* tii_; 52 AliasAnalysis *aa_; 53 LiveVariables* lv_; 54 SlotIndexes* indexes_; 55 56 /// Special pool allocator for VNInfo's (LiveInterval val#). 57 /// 58 VNInfo::Allocator VNInfoAllocator; 59 60 typedef DenseMap<unsigned, LiveInterval*> Reg2IntervalMap; 61 Reg2IntervalMap r2iMap_; 62 63 /// allocatableRegs_ - A bit vector of allocatable registers. 64 BitVector allocatableRegs_; 65 66 /// reservedRegs_ - A bit vector of reserved registers. 67 BitVector reservedRegs_; 68 69 /// RegMaskSlots - Sorted list of instructions with register mask operands. 70 /// Always use the 'r' slot, RegMasks are normal clobbers, not early 71 /// clobbers. 72 SmallVector<SlotIndex, 8> RegMaskSlots; 73 74 /// RegMaskBits - This vector is parallel to RegMaskSlots, it holds a 75 /// pointer to the corresponding register mask. This pointer can be 76 /// recomputed as: 77 /// 78 /// MI = Indexes->getInstructionFromIndex(RegMaskSlot[N]); 79 /// unsigned OpNum = findRegMaskOperand(MI); 80 /// RegMaskBits[N] = MI->getOperand(OpNum).getRegMask(); 81 /// 82 /// This is kept in a separate vector partly because some standard 83 /// libraries don't support lower_bound() with mixed objects, partly to 84 /// improve locality when searching in RegMaskSlots. 85 /// Also see the comment in LiveInterval::find(). 86 SmallVector<const uint32_t*, 8> RegMaskBits; 87 88 /// For each basic block number, keep (begin, size) pairs indexing into the 89 /// RegMaskSlots and RegMaskBits arrays. 90 /// Note that basic block numbers may not be layout contiguous, that's why 91 /// we can't just keep track of the first register mask in each basic 92 /// block. 93 SmallVector<std::pair<unsigned, unsigned>, 8> RegMaskBlocks; 94 95 public: 96 static char ID; // Pass identification, replacement for typeid 97 LiveIntervals() : MachineFunctionPass(ID) { 98 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry()); 99 } 100 101 // Calculate the spill weight to assign to a single instruction. 102 static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth); 103 104 typedef Reg2IntervalMap::iterator iterator; 105 typedef Reg2IntervalMap::const_iterator const_iterator; 106 const_iterator begin() const { return r2iMap_.begin(); } 107 const_iterator end() const { return r2iMap_.end(); } 108 iterator begin() { return r2iMap_.begin(); } 109 iterator end() { return r2iMap_.end(); } 110 unsigned getNumIntervals() const { return (unsigned)r2iMap_.size(); } 111 112 LiveInterval &getInterval(unsigned reg) { 113 Reg2IntervalMap::iterator I = r2iMap_.find(reg); 114 assert(I != r2iMap_.end() && "Interval does not exist for register"); 115 return *I->second; 116 } 117 118 const LiveInterval &getInterval(unsigned reg) const { 119 Reg2IntervalMap::const_iterator I = r2iMap_.find(reg); 120 assert(I != r2iMap_.end() && "Interval does not exist for register"); 121 return *I->second; 122 } 123 124 bool hasInterval(unsigned reg) const { 125 return r2iMap_.count(reg); 126 } 127 128 /// isAllocatable - is the physical register reg allocatable in the current 129 /// function? 130 bool isAllocatable(unsigned reg) const { 131 return allocatableRegs_.test(reg); 132 } 133 134 /// isReserved - is the physical register reg reserved in the current 135 /// function 136 bool isReserved(unsigned reg) const { 137 return reservedRegs_.test(reg); 138 } 139 140 /// getScaledIntervalSize - get the size of an interval in "units," 141 /// where every function is composed of one thousand units. This 142 /// measure scales properly with empty index slots in the function. 143 double getScaledIntervalSize(LiveInterval& I) { 144 return (1000.0 * I.getSize()) / indexes_->getIndexesLength(); 145 } 146 147 /// getFuncInstructionCount - Return the number of instructions in the 148 /// current function. 149 unsigned getFuncInstructionCount() { 150 return indexes_->getFunctionSize(); 151 } 152 153 /// getApproximateInstructionCount - computes an estimate of the number 154 /// of instructions in a given LiveInterval. 155 unsigned getApproximateInstructionCount(LiveInterval& I) { 156 double IntervalPercentage = getScaledIntervalSize(I) / 1000.0; 157 return (unsigned)(IntervalPercentage * indexes_->getFunctionSize()); 158 } 159 160 // Interval creation 161 LiveInterval &getOrCreateInterval(unsigned reg) { 162 Reg2IntervalMap::iterator I = r2iMap_.find(reg); 163 if (I == r2iMap_.end()) 164 I = r2iMap_.insert(std::make_pair(reg, createInterval(reg))).first; 165 return *I->second; 166 } 167 168 /// dupInterval - Duplicate a live interval. The caller is responsible for 169 /// managing the allocated memory. 170 LiveInterval *dupInterval(LiveInterval *li); 171 172 /// addLiveRangeToEndOfBlock - Given a register and an instruction, 173 /// adds a live range from that instruction to the end of its MBB. 174 LiveRange addLiveRangeToEndOfBlock(unsigned reg, 175 MachineInstr* startInst); 176 177 /// shrinkToUses - After removing some uses of a register, shrink its live 178 /// range to just the remaining uses. This method does not compute reaching 179 /// defs for new uses, and it doesn't remove dead defs. 180 /// Dead PHIDef values are marked as unused. 181 /// New dead machine instructions are added to the dead vector. 182 /// Return true if the interval may have been separated into multiple 183 /// connected components. 184 bool shrinkToUses(LiveInterval *li, 185 SmallVectorImpl<MachineInstr*> *dead = 0); 186 187 // Interval removal 188 189 void removeInterval(unsigned Reg) { 190 DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.find(Reg); 191 delete I->second; 192 r2iMap_.erase(I); 193 } 194 195 SlotIndexes *getSlotIndexes() const { 196 return indexes_; 197 } 198 199 /// isNotInMIMap - returns true if the specified machine instr has been 200 /// removed or was never entered in the map. 201 bool isNotInMIMap(const MachineInstr* Instr) const { 202 return !indexes_->hasIndex(Instr); 203 } 204 205 /// Returns the base index of the given instruction. 206 SlotIndex getInstructionIndex(const MachineInstr *instr) const { 207 return indexes_->getInstructionIndex(instr); 208 } 209 210 /// Returns the instruction associated with the given index. 211 MachineInstr* getInstructionFromIndex(SlotIndex index) const { 212 return indexes_->getInstructionFromIndex(index); 213 } 214 215 /// Return the first index in the given basic block. 216 SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const { 217 return indexes_->getMBBStartIdx(mbb); 218 } 219 220 /// Return the last index in the given basic block. 221 SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const { 222 return indexes_->getMBBEndIdx(mbb); 223 } 224 225 bool isLiveInToMBB(const LiveInterval &li, 226 const MachineBasicBlock *mbb) const { 227 return li.liveAt(getMBBStartIdx(mbb)); 228 } 229 230 bool isLiveOutOfMBB(const LiveInterval &li, 231 const MachineBasicBlock *mbb) const { 232 return li.liveAt(getMBBEndIdx(mbb).getPrevSlot()); 233 } 234 235 MachineBasicBlock* getMBBFromIndex(SlotIndex index) const { 236 return indexes_->getMBBFromIndex(index); 237 } 238 239 SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) { 240 return indexes_->insertMachineInstrInMaps(MI); 241 } 242 243 void RemoveMachineInstrFromMaps(MachineInstr *MI) { 244 indexes_->removeMachineInstrFromMaps(MI); 245 } 246 247 void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) { 248 indexes_->replaceMachineInstrInMaps(MI, NewMI); 249 } 250 251 bool findLiveInMBBs(SlotIndex Start, SlotIndex End, 252 SmallVectorImpl<MachineBasicBlock*> &MBBs) const { 253 return indexes_->findLiveInMBBs(Start, End, MBBs); 254 } 255 256 VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; } 257 258 virtual void getAnalysisUsage(AnalysisUsage &AU) const; 259 virtual void releaseMemory(); 260 261 /// runOnMachineFunction - pass entry point 262 virtual bool runOnMachineFunction(MachineFunction&); 263 264 /// print - Implement the dump method. 265 virtual void print(raw_ostream &O, const Module* = 0) const; 266 267 /// isReMaterializable - Returns true if every definition of MI of every 268 /// val# of the specified interval is re-materializable. Also returns true 269 /// by reference if all of the defs are load instructions. 270 bool isReMaterializable(const LiveInterval &li, 271 const SmallVectorImpl<LiveInterval*> *SpillIs, 272 bool &isLoad); 273 274 /// intervalIsInOneMBB - If LI is confined to a single basic block, return 275 /// a pointer to that block. If LI is live in to or out of any block, 276 /// return NULL. 277 MachineBasicBlock *intervalIsInOneMBB(const LiveInterval &LI) const; 278 279 /// addKillFlags - Add kill flags to any instruction that kills a virtual 280 /// register. 281 void addKillFlags(); 282 283 /// handleMove - call this method to notify LiveIntervals that 284 /// instruction 'mi' has been moved within a basic block. This will update 285 /// the live intervals for all operands of mi. Moves between basic blocks 286 /// are not supported. 287 void handleMove(MachineInstr* MI); 288 289 /// moveIntoBundle - Update intervals for operands of MI so that they 290 /// begin/end on the SlotIndex for BundleStart. 291 /// 292 /// Requires MI and BundleStart to have SlotIndexes, and assumes 293 /// existing liveness is accurate. BundleStart should be the first 294 /// instruction in the Bundle. 295 void handleMoveIntoBundle(MachineInstr* MI, MachineInstr* BundleStart); 296 297 // Register mask functions. 298 // 299 // Machine instructions may use a register mask operand to indicate that a 300 // large number of registers are clobbered by the instruction. This is 301 // typically used for calls. 302 // 303 // For compile time performance reasons, these clobbers are not recorded in 304 // the live intervals for individual physical registers. Instead, 305 // LiveIntervalAnalysis maintains a sorted list of instructions with 306 // register mask operands. 307 308 /// getRegMaskSlots - Returns a sorted array of slot indices of all 309 /// instructions with register mask operands. 310 ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; } 311 312 /// getRegMaskSlotsInBlock - Returns a sorted array of slot indices of all 313 /// instructions with register mask operands in the basic block numbered 314 /// MBBNum. 315 ArrayRef<SlotIndex> getRegMaskSlotsInBlock(unsigned MBBNum) const { 316 std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum]; 317 return getRegMaskSlots().slice(P.first, P.second); 318 } 319 320 /// getRegMaskBits() - Returns an array of register mask pointers 321 /// corresponding to getRegMaskSlots(). 322 ArrayRef<const uint32_t*> getRegMaskBits() const { return RegMaskBits; } 323 324 /// getRegMaskBitsInBlock - Returns an array of mask pointers corresponding 325 /// to getRegMaskSlotsInBlock(MBBNum). 326 ArrayRef<const uint32_t*> getRegMaskBitsInBlock(unsigned MBBNum) const { 327 std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum]; 328 return getRegMaskBits().slice(P.first, P.second); 329 } 330 331 /// checkRegMaskInterference - Test if LI is live across any register mask 332 /// instructions, and compute a bit mask of physical registers that are not 333 /// clobbered by any of them. 334 /// 335 /// Returns false if LI doesn't cross any register mask instructions. In 336 /// that case, the bit vector is not filled in. 337 bool checkRegMaskInterference(LiveInterval &LI, 338 BitVector &UsableRegs); 339 340 private: 341 /// computeIntervals - Compute live intervals. 342 void computeIntervals(); 343 344 /// handleRegisterDef - update intervals for a register def 345 /// (calls handlePhysicalRegisterDef and 346 /// handleVirtualRegisterDef) 347 void handleRegisterDef(MachineBasicBlock *MBB, 348 MachineBasicBlock::iterator MI, 349 SlotIndex MIIdx, 350 MachineOperand& MO, unsigned MOIdx); 351 352 /// isPartialRedef - Return true if the specified def at the specific index 353 /// is partially re-defining the specified live interval. A common case of 354 /// this is a definition of the sub-register. 355 bool isPartialRedef(SlotIndex MIIdx, MachineOperand &MO, 356 LiveInterval &interval); 357 358 /// handleVirtualRegisterDef - update intervals for a virtual 359 /// register def 360 void handleVirtualRegisterDef(MachineBasicBlock *MBB, 361 MachineBasicBlock::iterator MI, 362 SlotIndex MIIdx, MachineOperand& MO, 363 unsigned MOIdx, 364 LiveInterval& interval); 365 366 /// handlePhysicalRegisterDef - update intervals for a physical register 367 /// def. 368 void handlePhysicalRegisterDef(MachineBasicBlock* mbb, 369 MachineBasicBlock::iterator mi, 370 SlotIndex MIIdx, MachineOperand& MO, 371 LiveInterval &interval); 372 373 /// handleLiveInRegister - Create interval for a livein register. 374 void handleLiveInRegister(MachineBasicBlock* mbb, 375 SlotIndex MIIdx, 376 LiveInterval &interval); 377 378 /// getReMatImplicitUse - If the remat definition MI has one (for now, we 379 /// only allow one) virtual register operand, then its uses are implicitly 380 /// using the register. Returns the virtual register. 381 unsigned getReMatImplicitUse(const LiveInterval &li, 382 MachineInstr *MI) const; 383 384 /// isValNoAvailableAt - Return true if the val# of the specified interval 385 /// which reaches the given instruction also reaches the specified use 386 /// index. 387 bool isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI, 388 SlotIndex UseIdx) const; 389 390 /// isReMaterializable - Returns true if the definition MI of the specified 391 /// val# of the specified interval is re-materializable. Also returns true 392 /// by reference if the def is a load. 393 bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo, 394 MachineInstr *MI, 395 const SmallVectorImpl<LiveInterval*> *SpillIs, 396 bool &isLoad); 397 398 static LiveInterval* createInterval(unsigned Reg); 399 400 void printInstrs(raw_ostream &O) const; 401 void dumpInstrs() const; 402 403 class HMEditor; 404 }; 405 } // End llvm namespace 406 407 #endif 408
