| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 78 // STriw_pred [R30], ofst, SrcReg;
84 int SrcReg = MI->getOperand(2).getReg();
85 assert(Hexagon::PredRegsRegClass.contains(SrcReg) &&
96 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
105 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
113 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
|
| HexagonPeephole.cpp | 132 unsigned SrcReg = Src.getReg();
135 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
139 PeepholeMap[DstReg] = SrcReg;
150 unsigned SrcReg = Src.getReg();
153 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
157 PeepholeMap[DstReg] = SrcReg;
173 unsigned SrcReg = Src.getReg();
175 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
177 if (unsigned PeepholeSrc = PeepholeMap.lookup(SrcReg)) {
|
| /external/llvm/lib/CodeGen/ |
| RegisterCoalescer.h | 36 /// SrcReg - the virtual register that will be coalesced into dstReg.
37 unsigned SrcReg;
39 /// subReg_ - The subregister index of srcReg in DstReg. It is possible the
40 /// coalesce SrcReg into a subreg of the larger DstReg when DstReg is a
50 /// Flipped - True when DstReg and SrcReg are reversed from the original
60 : TII(tii), TRI(tri), DstReg(0), SrcReg(0), SubIdx(0),
67 /// flip - Swap SrcReg and DstReg. Return false if swapping is impossible
95 unsigned getSrcReg() const { return SrcReg; }
97 /// getSubIdx - Return the subregister index in DstReg that SrcReg will be
|
| OptimizePHIs.cpp | 99 unsigned SrcReg = MI->getOperand(i).getReg();
100 if (SrcReg == DstReg)
102 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
120 SingleValReg = SrcReg;
|
| MachineSSAUpdater.cpp | 94 unsigned SrcReg = I->getOperand(i).getReg();
96 if (AVals[SrcBB] != SrcReg) {
|
| MachineSink.cpp | 119 unsigned SrcReg = MI->getOperand(1).getReg();
121 if (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
123 !MRI->hasOneNonDBGUse(SrcReg))
126 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
131 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
136 MRI->replaceRegWith(DstReg, SrcReg);
|
| PHIElimination.cpp | 179 unsigned SrcReg = MPhi->getOperand(i).getReg();
180 const MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
288 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
291 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
300 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
315 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
320 TII->get(TargetOpcode::COPY), IncomingReg).addReg(SrcReg, 0, SrcSubReg);
337 bool ValueIsUsed = VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)];
341 if (!ValueIsUsed && !LV->isLiveOut(SrcReg, opBlock)) {
349 if (Term != opBlock.end() && Term->readsRegister(SrcReg)) {
[all...] |
| PeepholeOptimizer.cpp | 131 unsigned SrcReg, DstReg, SubIdx;
132 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
136 TargetRegisterInfo::isPhysicalRegister(SrcReg))
139 MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(SrcReg);
159 UI = MRI->use_nodbg_begin(SrcReg);
232 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
338 unsigned SrcReg;
340 if (!TII->AnalyzeCompare(MI, SrcReg, CmpMask, CmpValue) ||
341 TargetRegisterInfo::isPhysicalRegister(SrcReg))
345 if (TII->OptimizeCompareInstr(MI, SrcReg, CmpMask, CmpValue, MRI))
[all...] |
| MachineCSE.cpp | 137 unsigned SrcReg = DefMI->getOperand(1).getReg();
138 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
142 if (!MRI->constrainRegClass(SrcReg, MRI->getRegClass(Reg)))
146 MO.setReg(SrcReg);
147 MRI->clearKillFlags(SrcReg);
|
| StrongPHIElimination.cpp | 249 unsigned SrcReg = SrcMO.getReg();
250 addReg(SrcReg);
251 unionRegs(DestReg, SrcReg);
253 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
291 unsigned SrcReg = BBI->getOperand(i).getReg();
292 addReg(SrcReg);
293 unionRegs(DestReg, SrcReg);
308 unsigned SrcReg = PHI->getOperand(1).getReg();
309 unsigned SrcColor = getRegColor(SrcReg);
312 NewReg = SrcReg;
[all...] |
| TailDuplication.cpp | 239 unsigned SrcReg = LI->second[j].second;
240 SSAUpdate.AddAvailableValue(SrcBB, SrcReg);
352 unsigned SrcReg = MI.getOperand(i).getReg();
353 UsedByPhi->insert(SrcReg);
386 unsigned SrcReg = MI->getOperand(SrcOpIdx).getReg();
388 LocalVRMap.insert(std::make_pair(DefReg, SrcReg));
393 Copies.push_back(std::make_pair(NewDef, SrcReg));
494 unsigned SrcReg = LI->second[j].second;
496 II->getOperand(Idx).setReg(SrcReg);
500 II->addOperand(MachineOperand::CreateReg(SrcReg, false))
[all...] |
| TwoAddressInstructionPass.cpp | 409 unsigned &SrcReg, unsigned &DstReg,
411 SrcReg = 0;
415 SrcReg = MI.getOperand(1).getReg();
418 SrcReg = MI.getOperand(2).getReg();
422 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
458 unsigned SrcReg, DstReg;
461 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
463 Reg = SrcReg;
526 unsigned SrcReg;
528 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
[all...] |
| RegisterCoalescer.cpp | 113 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
154 bool isWinToJoinCrossClass(unsigned SrcReg,
160 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
236 SrcReg = DstReg = SubIdx = 0;
313 SrcReg = Src;
322 std::swap(SrcReg, DstReg);
334 // Find the virtual register that is SrcReg.
335 if (Dst == SrcReg) {
338 } else if (Src != SrcReg) {
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsExpandPseudo.cpp | 110 unsigned SrcReg = I->getOperand(1).getReg();
114 const uint16_t* SubReg = TM.getRegisterInfo()->getSubRegisters(SrcReg);
|
| MipsISelDAGToDAG.cpp | 519 unsigned RdhwrOpc, SrcReg, DestReg;
523 SrcReg = Mips::HWR29;
527 SrcReg = Mips::HWR29_64;
534 CurDAG->getRegister(SrcReg, PtrVT));
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 304 unsigned SrcReg = ValueMap[V];
305 if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
309 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
341 unsigned SrcReg = ValueMap[V];
342 if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
346 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2ITBlockPass.cpp | 122 unsigned SrcReg = MI->getOperand(1).getReg();
125 if (Uses.count(DstReg) || Defs.count(SrcReg))
|
| ARMExpandPseudoInsts.cpp | 462 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
464 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
478 MIB->addRegisterKilled(SrcReg, TRI, true);
592 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
594 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
605 MIB->addRegisterKilled(SrcReg, TRI, true);
[all...] |
| ARMAsmPrinter.cpp | [all...] |
| ARMFastISel.cpp | 186 bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
192 unsigned ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT, bool isZExt);
196 unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
197 unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
486 unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
492 .addReg(SrcReg));
496 unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
502 .addReg(SrcReg));
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 378 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
392 unsigned SrcReg = MI.getOperand(0).getReg();
395 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg.
397 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
401 if (SrcReg != PPC::CR0)
405 .addImm(getPPCRegisterNumbering(SrcReg) * 4)
|
| PPCFrameLowering.cpp | 131 unsigned SrcReg = MI->getOperand(1).getReg();
135 if (DstReg != SrcReg)
137 .addReg(SrcReg)
141 .addReg(SrcReg, RegState::Kill)
144 if (DstReg != SrcReg)
146 .addReg(SrcReg)
150 .addReg(SrcReg, RegState::Kill)
153 if (DstReg != SrcReg)
155 .addReg(SrcReg)
159 .addReg(SrcReg, RegState::Kill
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 69 unsigned SrcReg = MI.getOperand(OpNum).getReg();
71 if (X86II::isX86_64ExtendedReg(SrcReg))
566 unsigned SrcReg = MI.getOperand(i).getReg();
567 if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | [all...] |
