1 //===- FastISelEmitter.cpp - Generate an instruction selector -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This tablegen backend emits code for use by the "fast" instruction 11 // selection algorithm. See the comments at the top of 12 // lib/CodeGen/SelectionDAG/FastISel.cpp for background. 13 // 14 // This file scans through the target's tablegen instruction-info files 15 // and extracts instructions with obvious-looking patterns, and it emits 16 // code to look up these instructions by type and operator. 17 // 18 //===----------------------------------------------------------------------===// 19 20 #include "FastISelEmitter.h" 21 #include "llvm/TableGen/Error.h" 22 #include "llvm/TableGen/Record.h" 23 #include "llvm/ADT/SmallString.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/ErrorHandling.h" 26 using namespace llvm; 27 28 namespace { 29 30 /// InstructionMemo - This class holds additional information about an 31 /// instruction needed to emit code for it. 32 /// 33 struct InstructionMemo { 34 std::string Name; 35 const CodeGenRegisterClass *RC; 36 std::string SubRegNo; 37 std::vector<std::string>* PhysRegs; 38 }; 39 40 /// ImmPredicateSet - This uniques predicates (represented as a string) and 41 /// gives them unique (small) integer ID's that start at 0. 42 class ImmPredicateSet { 43 DenseMap<TreePattern *, unsigned> ImmIDs; 44 std::vector<TreePredicateFn> PredsByName; 45 public: 46 47 unsigned getIDFor(TreePredicateFn Pred) { 48 unsigned &Entry = ImmIDs[Pred.getOrigPatFragRecord()]; 49 if (Entry == 0) { 50 PredsByName.push_back(Pred); 51 Entry = PredsByName.size(); 52 } 53 return Entry-1; 54 } 55 56 const TreePredicateFn &getPredicate(unsigned i) { 57 assert(i < PredsByName.size()); 58 return PredsByName[i]; 59 } 60 61 typedef std::vector<TreePredicateFn>::const_iterator iterator; 62 iterator begin() const { return PredsByName.begin(); } 63 iterator end() const { return PredsByName.end(); } 64 65 }; 66 67 /// OperandsSignature - This class holds a description of a list of operand 68 /// types. It has utility methods for emitting text based on the operands. 69 /// 70 struct OperandsSignature { 71 class OpKind { 72 enum { OK_Reg, OK_FP, OK_Imm, OK_Invalid = -1 }; 73 char Repr; 74 public: 75 76 OpKind() : Repr(OK_Invalid) {} 77 78 bool operator<(OpKind RHS) const { return Repr < RHS.Repr; } 79 bool operator==(OpKind RHS) const { return Repr == RHS.Repr; } 80 81 static OpKind getReg() { OpKind K; K.Repr = OK_Reg; return K; } 82 static OpKind getFP() { OpKind K; K.Repr = OK_FP; return K; } 83 static OpKind getImm(unsigned V) { 84 assert((unsigned)OK_Imm+V < 128 && 85 "Too many integer predicates for the 'Repr' char"); 86 OpKind K; K.Repr = OK_Imm+V; return K; 87 } 88 89 bool isReg() const { return Repr == OK_Reg; } 90 bool isFP() const { return Repr == OK_FP; } 91 bool isImm() const { return Repr >= OK_Imm; } 92 93 unsigned getImmCode() const { assert(isImm()); return Repr-OK_Imm; } 94 95 void printManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates, 96 bool StripImmCodes) const { 97 if (isReg()) 98 OS << 'r'; 99 else if (isFP()) 100 OS << 'f'; 101 else { 102 OS << 'i'; 103 if (!StripImmCodes) 104 if (unsigned Code = getImmCode()) 105 OS << "_" << ImmPredicates.getPredicate(Code-1).getFnName(); 106 } 107 } 108 }; 109 110 111 SmallVector<OpKind, 3> Operands; 112 113 bool operator<(const OperandsSignature &O) const { 114 return Operands < O.Operands; 115 } 116 bool operator==(const OperandsSignature &O) const { 117 return Operands == O.Operands; 118 } 119 120 bool empty() const { return Operands.empty(); } 121 122 bool hasAnyImmediateCodes() const { 123 for (unsigned i = 0, e = Operands.size(); i != e; ++i) 124 if (Operands[i].isImm() && Operands[i].getImmCode() != 0) 125 return true; 126 return false; 127 } 128 129 /// getWithoutImmCodes - Return a copy of this with any immediate codes forced 130 /// to zero. 131 OperandsSignature getWithoutImmCodes() const { 132 OperandsSignature Result; 133 for (unsigned i = 0, e = Operands.size(); i != e; ++i) 134 if (!Operands[i].isImm()) 135 Result.Operands.push_back(Operands[i]); 136 else 137 Result.Operands.push_back(OpKind::getImm(0)); 138 return Result; 139 } 140 141 void emitImmediatePredicate(raw_ostream &OS, ImmPredicateSet &ImmPredicates) { 142 bool EmittedAnything = false; 143 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 144 if (!Operands[i].isImm()) continue; 145 146 unsigned Code = Operands[i].getImmCode(); 147 if (Code == 0) continue; 148 149 if (EmittedAnything) 150 OS << " &&\n "; 151 152 TreePredicateFn PredFn = ImmPredicates.getPredicate(Code-1); 153 154 // Emit the type check. 155 OS << "VT == " 156 << getEnumName(PredFn.getOrigPatFragRecord()->getTree(0)->getType(0)) 157 << " && "; 158 159 160 OS << PredFn.getFnName() << "(imm" << i <<')'; 161 EmittedAnything = true; 162 } 163 } 164 165 /// initialize - Examine the given pattern and initialize the contents 166 /// of the Operands array accordingly. Return true if all the operands 167 /// are supported, false otherwise. 168 /// 169 bool initialize(TreePatternNode *InstPatNode, const CodeGenTarget &Target, 170 MVT::SimpleValueType VT, 171 ImmPredicateSet &ImmediatePredicates) { 172 if (InstPatNode->isLeaf()) 173 return false; 174 175 if (InstPatNode->getOperator()->getName() == "imm") { 176 Operands.push_back(OpKind::getImm(0)); 177 return true; 178 } 179 180 if (InstPatNode->getOperator()->getName() == "fpimm") { 181 Operands.push_back(OpKind::getFP()); 182 return true; 183 } 184 185 const CodeGenRegisterClass *DstRC = 0; 186 187 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) { 188 TreePatternNode *Op = InstPatNode->getChild(i); 189 190 // Handle imm operands specially. 191 if (!Op->isLeaf() && Op->getOperator()->getName() == "imm") { 192 unsigned PredNo = 0; 193 if (!Op->getPredicateFns().empty()) { 194 TreePredicateFn PredFn = Op->getPredicateFns()[0]; 195 // If there is more than one predicate weighing in on this operand 196 // then we don't handle it. This doesn't typically happen for 197 // immediates anyway. 198 if (Op->getPredicateFns().size() > 1 || 199 !PredFn.isImmediatePattern()) 200 return false; 201 // Ignore any instruction with 'FastIselShouldIgnore', these are 202 // not needed and just bloat the fast instruction selector. For 203 // example, X86 doesn't need to generate code to match ADD16ri8 since 204 // ADD16ri will do just fine. 205 Record *Rec = PredFn.getOrigPatFragRecord()->getRecord(); 206 if (Rec->getValueAsBit("FastIselShouldIgnore")) 207 return false; 208 209 PredNo = ImmediatePredicates.getIDFor(PredFn)+1; 210 } 211 212 // Handle unmatched immediate sizes here. 213 //if (Op->getType(0) != VT) 214 // return false; 215 216 Operands.push_back(OpKind::getImm(PredNo)); 217 continue; 218 } 219 220 221 // For now, filter out any operand with a predicate. 222 // For now, filter out any operand with multiple values. 223 if (!Op->getPredicateFns().empty() || Op->getNumTypes() != 1) 224 return false; 225 226 if (!Op->isLeaf()) { 227 if (Op->getOperator()->getName() == "fpimm") { 228 Operands.push_back(OpKind::getFP()); 229 continue; 230 } 231 // For now, ignore other non-leaf nodes. 232 return false; 233 } 234 235 assert(Op->hasTypeSet(0) && "Type infererence not done?"); 236 237 // For now, all the operands must have the same type (if they aren't 238 // immediates). Note that this causes us to reject variable sized shifts 239 // on X86. 240 if (Op->getType(0) != VT) 241 return false; 242 243 DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue()); 244 if (!OpDI) 245 return false; 246 Record *OpLeafRec = OpDI->getDef(); 247 248 // For now, the only other thing we accept is register operands. 249 const CodeGenRegisterClass *RC = 0; 250 if (OpLeafRec->isSubClassOf("RegisterOperand")) 251 OpLeafRec = OpLeafRec->getValueAsDef("RegClass"); 252 if (OpLeafRec->isSubClassOf("RegisterClass")) 253 RC = &Target.getRegisterClass(OpLeafRec); 254 else if (OpLeafRec->isSubClassOf("Register")) 255 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec); 256 else 257 return false; 258 259 // For now, this needs to be a register class of some sort. 260 if (!RC) 261 return false; 262 263 // For now, all the operands must have the same register class or be 264 // a strict subclass of the destination. 265 if (DstRC) { 266 if (DstRC != RC && !DstRC->hasSubClass(RC)) 267 return false; 268 } else 269 DstRC = RC; 270 Operands.push_back(OpKind::getReg()); 271 } 272 return true; 273 } 274 275 void PrintParameters(raw_ostream &OS) const { 276 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 277 if (Operands[i].isReg()) { 278 OS << "unsigned Op" << i << ", bool Op" << i << "IsKill"; 279 } else if (Operands[i].isImm()) { 280 OS << "uint64_t imm" << i; 281 } else if (Operands[i].isFP()) { 282 OS << "const ConstantFP *f" << i; 283 } else { 284 llvm_unreachable("Unknown operand kind!"); 285 } 286 if (i + 1 != e) 287 OS << ", "; 288 } 289 } 290 291 void PrintArguments(raw_ostream &OS, 292 const std::vector<std::string> &PR) const { 293 assert(PR.size() == Operands.size()); 294 bool PrintedArg = false; 295 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 296 if (PR[i] != "") 297 // Implicit physical register operand. 298 continue; 299 300 if (PrintedArg) 301 OS << ", "; 302 if (Operands[i].isReg()) { 303 OS << "Op" << i << ", Op" << i << "IsKill"; 304 PrintedArg = true; 305 } else if (Operands[i].isImm()) { 306 OS << "imm" << i; 307 PrintedArg = true; 308 } else if (Operands[i].isFP()) { 309 OS << "f" << i; 310 PrintedArg = true; 311 } else { 312 llvm_unreachable("Unknown operand kind!"); 313 } 314 } 315 } 316 317 void PrintArguments(raw_ostream &OS) const { 318 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 319 if (Operands[i].isReg()) { 320 OS << "Op" << i << ", Op" << i << "IsKill"; 321 } else if (Operands[i].isImm()) { 322 OS << "imm" << i; 323 } else if (Operands[i].isFP()) { 324 OS << "f" << i; 325 } else { 326 llvm_unreachable("Unknown operand kind!"); 327 } 328 if (i + 1 != e) 329 OS << ", "; 330 } 331 } 332 333 334 void PrintManglingSuffix(raw_ostream &OS, const std::vector<std::string> &PR, 335 ImmPredicateSet &ImmPredicates, 336 bool StripImmCodes = false) const { 337 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 338 if (PR[i] != "") 339 // Implicit physical register operand. e.g. Instruction::Mul expect to 340 // select to a binary op. On x86, mul may take a single operand with 341 // the other operand being implicit. We must emit something that looks 342 // like a binary instruction except for the very inner FastEmitInst_* 343 // call. 344 continue; 345 Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes); 346 } 347 } 348 349 void PrintManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates, 350 bool StripImmCodes = false) const { 351 for (unsigned i = 0, e = Operands.size(); i != e; ++i) 352 Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes); 353 } 354 }; 355 356 class FastISelMap { 357 typedef std::map<std::string, InstructionMemo> PredMap; 358 typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap; 359 typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap; 360 typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap; 361 typedef std::map<OperandsSignature, OpcodeTypeRetPredMap> 362 OperandsOpcodeTypeRetPredMap; 363 364 OperandsOpcodeTypeRetPredMap SimplePatterns; 365 366 std::map<OperandsSignature, std::vector<OperandsSignature> > 367 SignaturesWithConstantForms; 368 369 std::string InstNS; 370 ImmPredicateSet ImmediatePredicates; 371 public: 372 explicit FastISelMap(std::string InstNS); 373 374 void collectPatterns(CodeGenDAGPatterns &CGP); 375 void printImmediatePredicates(raw_ostream &OS); 376 void printFunctionDefinitions(raw_ostream &OS); 377 }; 378 379 } 380 381 static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) { 382 return CGP.getSDNodeInfo(Op).getEnumName(); 383 } 384 385 static std::string getLegalCName(std::string OpName) { 386 std::string::size_type pos = OpName.find("::"); 387 if (pos != std::string::npos) 388 OpName.replace(pos, 2, "_"); 389 return OpName; 390 } 391 392 FastISelMap::FastISelMap(std::string instns) 393 : InstNS(instns) { 394 } 395 396 static std::string PhyRegForNode(TreePatternNode *Op, 397 const CodeGenTarget &Target) { 398 std::string PhysReg; 399 400 if (!Op->isLeaf()) 401 return PhysReg; 402 403 DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue()); 404 Record *OpLeafRec = OpDI->getDef(); 405 if (!OpLeafRec->isSubClassOf("Register")) 406 return PhysReg; 407 408 PhysReg += static_cast<StringInit*>(OpLeafRec->getValue( \ 409 "Namespace")->getValue())->getValue(); 410 PhysReg += "::"; 411 PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName(); 412 return PhysReg; 413 } 414 415 void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) { 416 const CodeGenTarget &Target = CGP.getTargetInfo(); 417 418 // Determine the target's namespace name. 419 InstNS = Target.getInstNamespace() + "::"; 420 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!"); 421 422 // Scan through all the patterns and record the simple ones. 423 for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(), 424 E = CGP.ptm_end(); I != E; ++I) { 425 const PatternToMatch &Pattern = *I; 426 427 // For now, just look at Instructions, so that we don't have to worry 428 // about emitting multiple instructions for a pattern. 429 TreePatternNode *Dst = Pattern.getDstPattern(); 430 if (Dst->isLeaf()) continue; 431 Record *Op = Dst->getOperator(); 432 if (!Op->isSubClassOf("Instruction")) 433 continue; 434 CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op); 435 if (II.Operands.empty()) 436 continue; 437 438 // For now, ignore multi-instruction patterns. 439 bool MultiInsts = false; 440 for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) { 441 TreePatternNode *ChildOp = Dst->getChild(i); 442 if (ChildOp->isLeaf()) 443 continue; 444 if (ChildOp->getOperator()->isSubClassOf("Instruction")) { 445 MultiInsts = true; 446 break; 447 } 448 } 449 if (MultiInsts) 450 continue; 451 452 // For now, ignore instructions where the first operand is not an 453 // output register. 454 const CodeGenRegisterClass *DstRC = 0; 455 std::string SubRegNo; 456 if (Op->getName() != "EXTRACT_SUBREG") { 457 Record *Op0Rec = II.Operands[0].Rec; 458 if (Op0Rec->isSubClassOf("RegisterOperand")) 459 Op0Rec = Op0Rec->getValueAsDef("RegClass"); 460 if (!Op0Rec->isSubClassOf("RegisterClass")) 461 continue; 462 DstRC = &Target.getRegisterClass(Op0Rec); 463 if (!DstRC) 464 continue; 465 } else { 466 // If this isn't a leaf, then continue since the register classes are 467 // a bit too complicated for now. 468 if (!Dst->getChild(1)->isLeaf()) continue; 469 470 DefInit *SR = dynamic_cast<DefInit*>(Dst->getChild(1)->getLeafValue()); 471 if (SR) 472 SubRegNo = getQualifiedName(SR->getDef()); 473 else 474 SubRegNo = Dst->getChild(1)->getLeafValue()->getAsString(); 475 } 476 477 // Inspect the pattern. 478 TreePatternNode *InstPatNode = Pattern.getSrcPattern(); 479 if (!InstPatNode) continue; 480 if (InstPatNode->isLeaf()) continue; 481 482 // Ignore multiple result nodes for now. 483 if (InstPatNode->getNumTypes() > 1) continue; 484 485 Record *InstPatOp = InstPatNode->getOperator(); 486 std::string OpcodeName = getOpcodeName(InstPatOp, CGP); 487 MVT::SimpleValueType RetVT = MVT::isVoid; 488 if (InstPatNode->getNumTypes()) RetVT = InstPatNode->getType(0); 489 MVT::SimpleValueType VT = RetVT; 490 if (InstPatNode->getNumChildren()) { 491 assert(InstPatNode->getChild(0)->getNumTypes() == 1); 492 VT = InstPatNode->getChild(0)->getType(0); 493 } 494 495 // For now, filter out any instructions with predicates. 496 if (!InstPatNode->getPredicateFns().empty()) 497 continue; 498 499 // Check all the operands. 500 OperandsSignature Operands; 501 if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates)) 502 continue; 503 504 std::vector<std::string>* PhysRegInputs = new std::vector<std::string>(); 505 if (InstPatNode->getOperator()->getName() == "imm" || 506 InstPatNode->getOperator()->getName() == "fpimm") 507 PhysRegInputs->push_back(""); 508 else { 509 // Compute the PhysRegs used by the given pattern, and check that 510 // the mapping from the src to dst patterns is simple. 511 bool FoundNonSimplePattern = false; 512 unsigned DstIndex = 0; 513 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) { 514 std::string PhysReg = PhyRegForNode(InstPatNode->getChild(i), Target); 515 if (PhysReg.empty()) { 516 if (DstIndex >= Dst->getNumChildren() || 517 Dst->getChild(DstIndex)->getName() != 518 InstPatNode->getChild(i)->getName()) { 519 FoundNonSimplePattern = true; 520 break; 521 } 522 ++DstIndex; 523 } 524 525 PhysRegInputs->push_back(PhysReg); 526 } 527 528 if (Op->getName() != "EXTRACT_SUBREG" && DstIndex < Dst->getNumChildren()) 529 FoundNonSimplePattern = true; 530 531 if (FoundNonSimplePattern) 532 continue; 533 } 534 535 // Get the predicate that guards this pattern. 536 std::string PredicateCheck = Pattern.getPredicateCheck(); 537 538 // Ok, we found a pattern that we can handle. Remember it. 539 InstructionMemo Memo = { 540 Pattern.getDstPattern()->getOperator()->getName(), 541 DstRC, 542 SubRegNo, 543 PhysRegInputs 544 }; 545 546 if (SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck)) 547 throw TGError(Pattern.getSrcRecord()->getLoc(), 548 "Duplicate record in FastISel table!"); 549 550 SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo; 551 552 // If any of the operands were immediates with predicates on them, strip 553 // them down to a signature that doesn't have predicates so that we can 554 // associate them with the stripped predicate version. 555 if (Operands.hasAnyImmediateCodes()) { 556 SignaturesWithConstantForms[Operands.getWithoutImmCodes()] 557 .push_back(Operands); 558 } 559 } 560 } 561 562 void FastISelMap::printImmediatePredicates(raw_ostream &OS) { 563 if (ImmediatePredicates.begin() == ImmediatePredicates.end()) 564 return; 565 566 OS << "\n// FastEmit Immediate Predicate functions.\n"; 567 for (ImmPredicateSet::iterator I = ImmediatePredicates.begin(), 568 E = ImmediatePredicates.end(); I != E; ++I) { 569 OS << "static bool " << I->getFnName() << "(int64_t Imm) {\n"; 570 OS << I->getImmediatePredicateCode() << "\n}\n"; 571 } 572 573 OS << "\n\n"; 574 } 575 576 577 void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { 578 // Now emit code for all the patterns that we collected. 579 for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(), 580 OE = SimplePatterns.end(); OI != OE; ++OI) { 581 const OperandsSignature &Operands = OI->first; 582 const OpcodeTypeRetPredMap &OTM = OI->second; 583 584 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end(); 585 I != E; ++I) { 586 const std::string &Opcode = I->first; 587 const TypeRetPredMap &TM = I->second; 588 589 OS << "// FastEmit functions for " << Opcode << ".\n"; 590 OS << "\n"; 591 592 // Emit one function for each opcode,type pair. 593 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end(); 594 TI != TE; ++TI) { 595 MVT::SimpleValueType VT = TI->first; 596 const RetPredMap &RM = TI->second; 597 if (RM.size() != 1) { 598 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end(); 599 RI != RE; ++RI) { 600 MVT::SimpleValueType RetVT = RI->first; 601 const PredMap &PM = RI->second; 602 bool HasPred = false; 603 604 OS << "unsigned FastEmit_" 605 << getLegalCName(Opcode) 606 << "_" << getLegalCName(getName(VT)) 607 << "_" << getLegalCName(getName(RetVT)) << "_"; 608 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 609 OS << "("; 610 Operands.PrintParameters(OS); 611 OS << ") {\n"; 612 613 // Emit code for each possible instruction. There may be 614 // multiple if there are subtarget concerns. 615 for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); 616 PI != PE; ++PI) { 617 std::string PredicateCheck = PI->first; 618 const InstructionMemo &Memo = PI->second; 619 620 if (PredicateCheck.empty()) { 621 assert(!HasPred && 622 "Multiple instructions match, at least one has " 623 "a predicate and at least one doesn't!"); 624 } else { 625 OS << " if (" + PredicateCheck + ") {\n"; 626 OS << " "; 627 HasPred = true; 628 } 629 630 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) { 631 if ((*Memo.PhysRegs)[i] != "") 632 OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, " 633 << "TII.get(TargetOpcode::COPY), " 634 << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n"; 635 } 636 637 OS << " return FastEmitInst_"; 638 if (Memo.SubRegNo.empty()) { 639 Operands.PrintManglingSuffix(OS, *Memo.PhysRegs, 640 ImmediatePredicates, true); 641 OS << "(" << InstNS << Memo.Name << ", "; 642 OS << InstNS << Memo.RC->getName() << "RegisterClass"; 643 if (!Operands.empty()) 644 OS << ", "; 645 Operands.PrintArguments(OS, *Memo.PhysRegs); 646 OS << ");\n"; 647 } else { 648 OS << "extractsubreg(" << getName(RetVT); 649 OS << ", Op0, Op0IsKill, " << Memo.SubRegNo << ");\n"; 650 } 651 652 if (HasPred) 653 OS << " }\n"; 654 655 } 656 // Return 0 if none of the predicates were satisfied. 657 if (HasPred) 658 OS << " return 0;\n"; 659 OS << "}\n"; 660 OS << "\n"; 661 } 662 663 // Emit one function for the type that demultiplexes on return type. 664 OS << "unsigned FastEmit_" 665 << getLegalCName(Opcode) << "_" 666 << getLegalCName(getName(VT)) << "_"; 667 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 668 OS << "(MVT RetVT"; 669 if (!Operands.empty()) 670 OS << ", "; 671 Operands.PrintParameters(OS); 672 OS << ") {\nswitch (RetVT.SimpleTy) {\n"; 673 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end(); 674 RI != RE; ++RI) { 675 MVT::SimpleValueType RetVT = RI->first; 676 OS << " case " << getName(RetVT) << ": return FastEmit_" 677 << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT)) 678 << "_" << getLegalCName(getName(RetVT)) << "_"; 679 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 680 OS << "("; 681 Operands.PrintArguments(OS); 682 OS << ");\n"; 683 } 684 OS << " default: return 0;\n}\n}\n\n"; 685 686 } else { 687 // Non-variadic return type. 688 OS << "unsigned FastEmit_" 689 << getLegalCName(Opcode) << "_" 690 << getLegalCName(getName(VT)) << "_"; 691 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 692 OS << "(MVT RetVT"; 693 if (!Operands.empty()) 694 OS << ", "; 695 Operands.PrintParameters(OS); 696 OS << ") {\n"; 697 698 OS << " if (RetVT.SimpleTy != " << getName(RM.begin()->first) 699 << ")\n return 0;\n"; 700 701 const PredMap &PM = RM.begin()->second; 702 bool HasPred = false; 703 704 // Emit code for each possible instruction. There may be 705 // multiple if there are subtarget concerns. 706 for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE; 707 ++PI) { 708 std::string PredicateCheck = PI->first; 709 const InstructionMemo &Memo = PI->second; 710 711 if (PredicateCheck.empty()) { 712 assert(!HasPred && 713 "Multiple instructions match, at least one has " 714 "a predicate and at least one doesn't!"); 715 } else { 716 OS << " if (" + PredicateCheck + ") {\n"; 717 OS << " "; 718 HasPred = true; 719 } 720 721 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) { 722 if ((*Memo.PhysRegs)[i] != "") 723 OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, " 724 << "TII.get(TargetOpcode::COPY), " 725 << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n"; 726 } 727 728 OS << " return FastEmitInst_"; 729 730 if (Memo.SubRegNo.empty()) { 731 Operands.PrintManglingSuffix(OS, *Memo.PhysRegs, 732 ImmediatePredicates, true); 733 OS << "(" << InstNS << Memo.Name << ", "; 734 OS << InstNS << Memo.RC->getName() << "RegisterClass"; 735 if (!Operands.empty()) 736 OS << ", "; 737 Operands.PrintArguments(OS, *Memo.PhysRegs); 738 OS << ");\n"; 739 } else { 740 OS << "extractsubreg(RetVT, Op0, Op0IsKill, "; 741 OS << Memo.SubRegNo; 742 OS << ");\n"; 743 } 744 745 if (HasPred) 746 OS << " }\n"; 747 } 748 749 // Return 0 if none of the predicates were satisfied. 750 if (HasPred) 751 OS << " return 0;\n"; 752 OS << "}\n"; 753 OS << "\n"; 754 } 755 } 756 757 // Emit one function for the opcode that demultiplexes based on the type. 758 OS << "unsigned FastEmit_" 759 << getLegalCName(Opcode) << "_"; 760 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 761 OS << "(MVT VT, MVT RetVT"; 762 if (!Operands.empty()) 763 OS << ", "; 764 Operands.PrintParameters(OS); 765 OS << ") {\n"; 766 OS << " switch (VT.SimpleTy) {\n"; 767 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end(); 768 TI != TE; ++TI) { 769 MVT::SimpleValueType VT = TI->first; 770 std::string TypeName = getName(VT); 771 OS << " case " << TypeName << ": return FastEmit_" 772 << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_"; 773 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 774 OS << "(RetVT"; 775 if (!Operands.empty()) 776 OS << ", "; 777 Operands.PrintArguments(OS); 778 OS << ");\n"; 779 } 780 OS << " default: return 0;\n"; 781 OS << " }\n"; 782 OS << "}\n"; 783 OS << "\n"; 784 } 785 786 OS << "// Top-level FastEmit function.\n"; 787 OS << "\n"; 788 789 // Emit one function for the operand signature that demultiplexes based 790 // on opcode and type. 791 OS << "unsigned FastEmit_"; 792 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 793 OS << "(MVT VT, MVT RetVT, unsigned Opcode"; 794 if (!Operands.empty()) 795 OS << ", "; 796 Operands.PrintParameters(OS); 797 OS << ") {\n"; 798 799 // If there are any forms of this signature available that operand on 800 // constrained forms of the immediate (e.g. 32-bit sext immediate in a 801 // 64-bit operand), check them first. 802 803 std::map<OperandsSignature, std::vector<OperandsSignature> >::iterator MI 804 = SignaturesWithConstantForms.find(Operands); 805 if (MI != SignaturesWithConstantForms.end()) { 806 // Unique any duplicates out of the list. 807 std::sort(MI->second.begin(), MI->second.end()); 808 MI->second.erase(std::unique(MI->second.begin(), MI->second.end()), 809 MI->second.end()); 810 811 // Check each in order it was seen. It would be nice to have a good 812 // relative ordering between them, but we're not going for optimality 813 // here. 814 for (unsigned i = 0, e = MI->second.size(); i != e; ++i) { 815 OS << " if ("; 816 MI->second[i].emitImmediatePredicate(OS, ImmediatePredicates); 817 OS << ")\n if (unsigned Reg = FastEmit_"; 818 MI->second[i].PrintManglingSuffix(OS, ImmediatePredicates); 819 OS << "(VT, RetVT, Opcode"; 820 if (!MI->second[i].empty()) 821 OS << ", "; 822 MI->second[i].PrintArguments(OS); 823 OS << "))\n return Reg;\n\n"; 824 } 825 826 // Done with this, remove it. 827 SignaturesWithConstantForms.erase(MI); 828 } 829 830 OS << " switch (Opcode) {\n"; 831 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end(); 832 I != E; ++I) { 833 const std::string &Opcode = I->first; 834 835 OS << " case " << Opcode << ": return FastEmit_" 836 << getLegalCName(Opcode) << "_"; 837 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 838 OS << "(VT, RetVT"; 839 if (!Operands.empty()) 840 OS << ", "; 841 Operands.PrintArguments(OS); 842 OS << ");\n"; 843 } 844 OS << " default: return 0;\n"; 845 OS << " }\n"; 846 OS << "}\n"; 847 OS << "\n"; 848 } 849 850 // TODO: SignaturesWithConstantForms should be empty here. 851 } 852 853 void FastISelEmitter::run(raw_ostream &OS) { 854 const CodeGenTarget &Target = CGP.getTargetInfo(); 855 856 // Determine the target's namespace name. 857 std::string InstNS = Target.getInstNamespace() + "::"; 858 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!"); 859 860 EmitSourceFileHeader("\"Fast\" Instruction Selector for the " + 861 Target.getName() + " target", OS); 862 863 FastISelMap F(InstNS); 864 F.collectPatterns(CGP); 865 F.printImmediatePredicates(OS); 866 F.printFunctionDefinitions(OS); 867 } 868 869 FastISelEmitter::FastISelEmitter(RecordKeeper &R) 870 : Records(R), CGP(R) { 871 } 872 873