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Searched
defs:SubRegs
(Results
1 - 5
of
5
) sorted by null
/external/llvm/lib/Target/Mips/
MipsFrameLowering.cpp
221
const uint16_t *
SubRegs
= RegInfo->getSubRegisters(Reg);
224
MachineLocation SrcML0(*
SubRegs
);
225
MachineLocation SrcML1(*(
SubRegs
+ 1));
/external/llvm/include/llvm/MC/
MCRegisterInfo.h
102
/// alias EAX. The
SubRegs
field is a zero terminated array of registers that
111
uint32_t
SubRegs
; // Sub-register set, described above
258
return RegLists + get(RegNo).
SubRegs
;
/external/llvm/utils/TableGen/
CodeGenRegisters.h
109
return
SubRegs
;
158
SubRegMap
SubRegs
;
CodeGenRegisters.cpp
154
for (SubRegMap::const_iterator I =
SubRegs
.begin(), E =
SubRegs
.end();
157
// Only create a unit if no other
subregs
have units.
175
return
SubRegs
;
178
std::vector<Record*> SubList = TheDef->getValueAsListOfDefs("
SubRegs
");
182
" SubRegIndices doesn't match
SubRegs
");
184
// First insert the direct
subregs
and make sure they are fully indexed.
190
if (!
SubRegs
.insert(std::make_pair(Idx, SR)).second)
195
// Keep track of inherited
subregs
and how they can be reached.
198
// Clone inherited
subregs
and place duplicate entries in Orphans
[
all
...]
/external/llvm/lib/Target/ARM/
ARMBaseInstrInfo.cpp
685
unsigned
SubRegs
= 0;
690
Opc = ARM::VORRq, BeginIdx = ARM::qsub_0,
SubRegs
= 2;
692
Opc = ARM::VORRq, BeginIdx = ARM::qsub_0,
SubRegs
= 4;
695
Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0,
SubRegs
= 2;
697
Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0,
SubRegs
= 3;
699
Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0,
SubRegs
= 4;
702
Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0,
SubRegs
= 2, Spacing = 2;
704
Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0,
SubRegs
= 3, Spacing = 2;
706
Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0,
SubRegs
= 4, Spacing = 2;
711
for (unsigned i = 0; i !=
SubRegs
; ++i)
[
all
...]
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