1 /* 2 * SdioDrv.c 3 * 4 * Copyright(c) 1998 - 2009 Texas Instruments. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name Texas Instruments nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <linux/kernel.h> 35 #include <linux/module.h> 36 #include <linux/version.h> 37 #include <linux/moduleparam.h> 38 #include <linux/delay.h> 39 #include <linux/interrupt.h> 40 #include <linux/slab.h> 41 #include <linux/types.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/platform_device.h> 44 #include <linux/i2c/twl4030.h> 45 #include <linux/errno.h> 46 #include <linux/clk.h> 47 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 31)) 48 #include <plat/hardware.h> 49 #include <plat/board.h> 50 #include <plat/clock.h> 51 #include <plat/dma.h> 52 #include <plat/io.h> 53 #include <plat/resource.h> 54 #define IO_ADDRESS(pa) OMAP2_L4_IO_ADDRESS(pa) 55 #else 56 #include <mach/hardware.h> 57 #include <mach/board.h> 58 #include <mach/clock.h> 59 #include <mach/dma.h> 60 #include <mach/io.h> 61 #include <mach/resource.h> 62 #endif 63 typedef void *TI_HANDLE; 64 #include "host_platform.h" 65 #include "SdioDrvDbg.h" 66 #include "SdioDrv.h" 67 68 /* #define TI_SDIO_DEBUG */ 69 70 #ifndef CONFIG_MMC_EMBEDDED_SDIO 71 72 #define SDIOWQ_NAME "sdio_wq" 73 74 /* 75 * HSMMC Address and DMA Settings 76 */ 77 static unsigned long TIWLAN_MMC_CONTROLLER = 2; /* MMC3 */ 78 static unsigned long TIWLAN_MMC_CONTROLLER_BASE_ADDR = OMAP_HSMMC3_BASE; 79 #define TIWLAN_MMC_CONTROLLER_BASE_SIZE 512 80 #define TIWLAN_MMC_MAX_DMA 8192 81 static unsigned long TIWLAN_MMC_DMA_TX = OMAP34XX_DMA_MMC3_TX; 82 static unsigned long TIWLAN_MMC_DMA_RX = OMAP34XX_DMA_MMC3_RX; 83 static unsigned long OMAP_MMC_IRQ = INT_MMC3_IRQ; 84 85 #define OMAP_MMC_MASTER_CLOCK 96000000 86 /* 87 * HSMMC Host Controller Registers 88 */ 89 #define OMAP_HSMMC_SYSCONFIG 0x0010 90 #define OMAP_HSMMC_SYSSTATUS 0x0014 91 #define OMAP_HSMMC_CSRE 0x0024 92 #define OMAP_HSMMC_SYSTEST 0x0028 93 #define OMAP_HSMMC_CON 0x002C 94 #define OMAP_HSMMC_BLK 0x0104 95 #define OMAP_HSMMC_ARG 0x0108 96 #define OMAP_HSMMC_CMD 0x010C 97 #define OMAP_HSMMC_RSP10 0x0110 98 #define OMAP_HSMMC_RSP32 0x0114 99 #define OMAP_HSMMC_RSP54 0x0118 100 #define OMAP_HSMMC_RSP76 0x011C 101 #define OMAP_HSMMC_DATA 0x0120 102 #define OMAP_HSMMC_PSTATE 0x0124 103 #define OMAP_HSMMC_HCTL 0x0128 104 #define OMAP_HSMMC_SYSCTL 0x012C 105 #define OMAP_HSMMC_STAT 0x0130 106 #define OMAP_HSMMC_IE 0x0134 107 #define OMAP_HSMMC_ISE 0x0138 108 #define OMAP_HSMMC_AC12 0x013C 109 #define OMAP_HSMMC_CAPA 0x0140 110 #define OMAP_HSMMC_CUR_CAPA 0x0148 111 #define OMAP_HSMMC_REV 0x01FC 112 113 #define VS18 (1 << 26) 114 #define VS30 (1 << 25) 115 #define SRA (1 << 24) 116 #define SDVS18 (0x5 << 9) 117 #define SDVS30 (0x6 << 9) 118 #define SDVSCLR 0xFFFFF1FF 119 #define SDVSDET 0x00000400 120 #define SIDLE_MODE (0x2 << 3) 121 #define AUTOIDLE 0x1 122 #define SDBP (1 << 8) 123 #define DTO 0xE 124 #define ICE 0x1 125 #define ICS 0x2 126 #define CEN (1 << 2) 127 #define CLKD_MASK 0x0000FFC0 128 #define IE_EN_MASK 0x317F0137 129 #define INIT_STREAM (1 << 1) 130 #define DP_SELECT (1 << 21) 131 #define DDIR (1 << 4) 132 #define DMA_EN 0x1 133 #define MSBS (1 << 5) 134 #define BCE (1 << 1) 135 #define ONE_BIT (~(0x2)) 136 #define EIGHT_BIT (~(0x20)) 137 #define CC 0x1 138 #define TC 0x02 139 #define OD 0x1 140 #define BRW 0x400 141 #define BRR 0x800 142 #define BRE (1 << 11) 143 #define BWE (1 << 10) 144 #define SBGR (1 << 16) 145 #define CT (1 << 17) 146 #define SDIO_READ (1 << 31) 147 #define SDIO_BLKMODE (1 << 27) 148 #define OMAP_HSMMC_ERR (1 << 15) /* Any error */ 149 #define OMAP_HSMMC_CMD_TIMEOUT (1 << 16) /* Com mand response time-out */ 150 #define OMAP_HSMMC_DATA_TIMEOUT (1 << 20) /* Data response time-out */ 151 #define OMAP_HSMMC_CMD_CRC (1 << 17) /* Command CRC error */ 152 #define OMAP_HSMMC_DATA_CRC (1 << 21) /* Date CRC error */ 153 #define OMAP_HSMMC_CARD_ERR (1 << 28) /* Card ERR */ 154 #define OMAP_HSMMC_STAT_CLEAR 0xFFFFFFFF 155 #define INIT_STREAM_CMD 0x00000000 156 #define INT_CLEAR 0x00000000 157 #define BLK_CLEAR 0x00000000 158 159 /* SCM CONTROL_DEVCONF1 MMC1 overwrite but */ 160 161 #define MMC1_ACTIVE_OVERWRITE (1 << 31) 162 163 #define sdio_blkmode_regaddr 0x2000 164 #define sdio_blkmode_mask 0xFF00 165 166 #define IO_RW_DIRECT_MASK 0xF000FF00 167 #define IO_RW_DIRECT_ARG_MASK 0x80001A00 168 169 #define RMASK (MMC_RSP_MASK | MMC_RSP_CRC) 170 #define MMC_TIMEOUT_MS 100 /*on the new 2430 it was 20, i changed back to 100*//* obc */ 171 #define MMCA_VSN_4 4 172 173 #define VMMC1_DEV_GRP 0x27 174 #define P1_DEV_GRP 0x20 175 #define VMMC1_DEDICATED 0x2A 176 #define VSEL_3V 0x02 177 #define VSEL_18V 0x00 178 #define PBIAS_3V 0x03 179 #define PBIAS_18V 0x02 180 #define PBIAS_LITE 0x04A0 181 #define PBIAS_CLR 0x00 182 183 #define OMAP_MMC_REGS_BASE IO_ADDRESS(TIWLAN_MMC_CONTROLLER_BASE_ADDR) 184 185 /* 186 * MMC Host controller read/write API's. 187 */ 188 #define OMAP_HSMMC_READ_OFFSET(offset) (__raw_readl((OMAP_MMC_REGS_BASE) + (offset))) 189 #define OMAP_HSMMC_READ(reg) (__raw_readl((OMAP_MMC_REGS_BASE) + OMAP_HSMMC_##reg)) 190 #define OMAP_HSMMC_WRITE(reg, val) (__raw_writel((val), (OMAP_MMC_REGS_BASE) + OMAP_HSMMC_##reg)) 191 192 #define OMAP_HSMMC_SEND_COMMAND(cmd, arg) do \ 193 { \ 194 OMAP_HSMMC_WRITE(ARG, arg); \ 195 OMAP_HSMMC_WRITE(CMD, cmd); \ 196 } while (0) 197 198 #define OMAP_HSMMC_CMD52_WRITE ((SD_IO_RW_DIRECT << 24) | (OMAP_HSMMC_CMD_SHORT_RESPONSE << 16)) 199 #define OMAP_HSMMC_CMD52_READ (((SD_IO_RW_DIRECT << 24) | (OMAP_HSMMC_CMD_SHORT_RESPONSE << 16)) | DDIR) 200 #define OMAP_HSMMC_CMD53_WRITE (((SD_IO_RW_EXTENDED << 24) | (OMAP_HSMMC_CMD_SHORT_RESPONSE << 16)) | DP_SELECT) 201 #define OMAP_HSMMC_CMD53_READ (((SD_IO_RW_EXTENDED << 24) | (OMAP_HSMMC_CMD_SHORT_RESPONSE << 16)) | DP_SELECT | DDIR) 202 #define OMAP_HSMMC_CMD53_READ_DMA (OMAP_HSMMC_CMD53_READ | DMA_EN) 203 #define OMAP_HSMMC_CMD53_WRITE_DMA (OMAP_HSMMC_CMD53_WRITE | DMA_EN) 204 205 /* Macros to build commands 52 and 53 in format according to SDIO spec */ 206 #define SDIO_CMD52_READ(v1,v2,v3,v4) (SDIO_RWFLAG(v1)|SDIO_FUNCN(v2)|SDIO_RAWFLAG(v3)| SDIO_ADDRREG(v4)) 207 #define SDIO_CMD52_WRITE(v1,v2,v3,v4,v5) (SDIO_RWFLAG(v1)|SDIO_FUNCN(v2)|SDIO_RAWFLAG(v3)| SDIO_ADDRREG(v4)|(v5)) 208 #define SDIO_CMD53_READ(v1,v2,v3,v4,v5,v6) (SDIO_RWFLAG(v1)|SDIO_FUNCN(v2)|SDIO_BLKM(v3)| SDIO_OPCODE(v4)|SDIO_ADDRREG(v5)|(v6&0x1ff)) 209 #define SDIO_CMD53_WRITE(v1,v2,v3,v4,v5,v6) (SDIO_RWFLAG(v1)|SDIO_FUNCN(v2)|SDIO_BLKM(v3)| SDIO_OPCODE(v4)|SDIO_ADDRREG(v5)|(v6&0x1ff)) 210 211 #define SDIODRV_MAX_LOOPS 50000 212 213 #define VMMC2_DEV_GRP 0x2B 214 #define VMMC2_DEDICATED 0x2E 215 #define VSEL_S2_18V 0x05 216 #define LDO_CLR 0x00 217 #define VSEL_S2_CLR 0x40 218 #define GPIO_0_BIT_POS 1 << 0 219 #define GPIO_1_BIT_POS 1 << 1 220 #define VSIM_DEV_GRP 0x37 221 #define VSIM_DEDICATED 0x3A 222 #define TWL4030_MODULE_PM_RECIEVER 0x13 223 224 typedef struct OMAP3430_sdiodrv 225 { 226 struct clk *fclk, *iclk, *dbclk; 227 int ifclks_enabled; 228 spinlock_t clk_lock; 229 int dma_tx_channel; 230 int dma_rx_channel; 231 int irq; 232 void (*BusTxnCB)(void* BusTxnHandle, int status); 233 void* BusTxnHandle; 234 unsigned int uBlkSize; 235 unsigned int uBlkSizeShift; 236 int async_status; 237 int (*wlanDrvIf_pm_resume)(void); 238 int (*wlanDrvIf_pm_suspend)(void); 239 struct device *dev; 240 dma_addr_t dma_read_addr; 241 size_t dma_read_size; 242 dma_addr_t dma_write_addr; 243 size_t dma_write_size; 244 struct workqueue_struct *sdio_wq; /* Work Queue */ 245 struct work_struct sdiodrv_work; 246 struct timer_list inact_timer; 247 int inact_timer_running; 248 } OMAP3430_sdiodrv_t; 249 250 struct omap_hsmmc_regs { 251 u32 hctl; 252 u32 capa; 253 u32 sysconfig; 254 u32 ise; 255 u32 ie; 256 u32 con; 257 u32 sysctl; 258 }; 259 static struct omap_hsmmc_regs hsmmc_ctx; 260 261 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 31)) 262 static struct platform_device dummy_pdev = { 263 .dev = { 264 .bus = &platform_bus_type, 265 }, 266 }; 267 #endif 268 269 #define SDIO_DRIVER_NAME "TIWLAN_SDIO" 270 271 module_param(g_sdio_debug_level, int, 0644); 272 MODULE_PARM_DESC(g_sdio_debug_level, "debug level"); 273 int g_sdio_debug_level = SDIO_DEBUGLEVEL_ERR; 274 EXPORT_SYMBOL(g_sdio_debug_level); 275 276 OMAP3430_sdiodrv_t g_drv; 277 278 static int sdiodrv_irq_requested = 0; 279 static int sdiodrv_iclk_got = 0; 280 static int sdiodrv_fclk_got = 0; 281 282 static void sdioDrv_hsmmc_save_ctx(void); 283 static void sdioDrv_hsmmc_restore_ctx(void); 284 static void sdiodrv_dma_shutdown(void); 285 static void sdioDrv_inact_timer(unsigned long); 286 287 #ifndef TI_SDIO_STANDALONE 288 void sdio_init( int sdcnum ) 289 { 290 if( sdcnum <= 0 ) 291 return; 292 TIWLAN_MMC_CONTROLLER = sdcnum - 1; 293 if( sdcnum == 2 ) { 294 TIWLAN_MMC_CONTROLLER_BASE_ADDR = OMAP_HSMMC2_BASE; 295 TIWLAN_MMC_DMA_TX = OMAP24XX_DMA_MMC2_TX; 296 TIWLAN_MMC_DMA_RX = OMAP24XX_DMA_MMC2_RX; 297 OMAP_MMC_IRQ = INT_MMC2_IRQ; 298 } 299 else if( sdcnum == 3 ) { 300 TIWLAN_MMC_CONTROLLER_BASE_ADDR = OMAP_HSMMC3_BASE; 301 TIWLAN_MMC_DMA_TX = OMAP34XX_DMA_MMC3_TX; 302 TIWLAN_MMC_DMA_RX = OMAP34XX_DMA_MMC3_RX; 303 OMAP_MMC_IRQ = INT_MMC3_IRQ; 304 } 305 } 306 #endif 307 308 static void sdioDrv_hsmmc_save_ctx(void) 309 { 310 /* MMC : context save */ 311 hsmmc_ctx.hctl = OMAP_HSMMC_READ(HCTL); 312 hsmmc_ctx.capa = OMAP_HSMMC_READ(CAPA); 313 hsmmc_ctx.sysconfig = OMAP_HSMMC_READ(SYSCONFIG); 314 hsmmc_ctx.ise = OMAP_HSMMC_READ(ISE); 315 hsmmc_ctx.ie = OMAP_HSMMC_READ(IE); 316 hsmmc_ctx.con = OMAP_HSMMC_READ(CON); 317 hsmmc_ctx.sysctl = OMAP_HSMMC_READ(SYSCTL); 318 OMAP_HSMMC_WRITE(ISE, 0); 319 OMAP_HSMMC_WRITE(IE, 0); 320 } 321 322 static void sdioDrv_hsmmc_restore_ctx(void) 323 { 324 /* MMC : context restore */ 325 OMAP_HSMMC_WRITE(HCTL, hsmmc_ctx.hctl); 326 OMAP_HSMMC_WRITE(CAPA, hsmmc_ctx.capa); 327 OMAP_HSMMC_WRITE(SYSCONFIG, hsmmc_ctx.sysconfig); 328 OMAP_HSMMC_WRITE(CON, hsmmc_ctx.con); 329 OMAP_HSMMC_WRITE(ISE, hsmmc_ctx.ise); 330 OMAP_HSMMC_WRITE(IE, hsmmc_ctx.ie); 331 OMAP_HSMMC_WRITE(SYSCTL, hsmmc_ctx.sysctl); 332 OMAP_HSMMC_WRITE(HCTL, OMAP_HSMMC_READ(HCTL) | SDBP); 333 } 334 335 static void sdioDrv_inact_timer(unsigned long data) 336 { 337 sdioDrv_clk_disable(); 338 g_drv.inact_timer_running = 0; 339 } 340 341 void sdioDrv_start_inact_timer(void) 342 { 343 mod_timer(&g_drv.inact_timer, jiffies + msecs_to_jiffies(1000)); 344 g_drv.inact_timer_running = 1; 345 } 346 347 void sdioDrv_cancel_inact_timer(void) 348 { 349 if(g_drv.inact_timer_running) { 350 del_timer_sync(&g_drv.inact_timer); 351 g_drv.inact_timer_running = 0; 352 } 353 } 354 355 void sdiodrv_task(struct work_struct *unused) 356 { 357 PDEBUG("sdiodrv_tasklet()\n"); 358 359 if (g_drv.dma_read_addr != 0) { 360 dma_unmap_single(g_drv.dev, g_drv.dma_read_addr, g_drv.dma_read_size, DMA_FROM_DEVICE); 361 g_drv.dma_read_addr = 0; 362 g_drv.dma_read_size = 0; 363 } 364 365 if (g_drv.dma_write_addr != 0) { 366 dma_unmap_single(g_drv.dev, g_drv.dma_write_addr, g_drv.dma_write_size, DMA_TO_DEVICE); 367 g_drv.dma_write_addr = 0; 368 g_drv.dma_write_size = 0; 369 } 370 371 if (g_drv.BusTxnCB != NULL) { 372 g_drv.BusTxnCB(g_drv.BusTxnHandle, g_drv.async_status); 373 } 374 } 375 376 irqreturn_t sdiodrv_irq(int irq, void *drv) 377 { 378 int status; 379 380 PDEBUG("sdiodrv_irq()\n"); 381 382 status = OMAP_HSMMC_READ(STAT); 383 OMAP_HSMMC_WRITE(ISE, 0); 384 g_drv.async_status = status & (OMAP_HSMMC_ERR); 385 if (g_drv.async_status) { 386 PERR("sdiodrv_irq: ERROR in STAT = 0x%x\n", status); 387 } 388 queue_work(g_drv.sdio_wq, &g_drv.sdiodrv_work); 389 return IRQ_HANDLED; 390 } 391 392 void sdiodrv_dma_read_cb(int lch, u16 ch_status, void *data) 393 { 394 PDEBUG("sdiodrv_dma_read_cb() channel=%d status=0x%x\n", lch, (int)ch_status); 395 396 g_drv.async_status = ch_status & (1 << 7); 397 398 queue_work(g_drv.sdio_wq, &g_drv.sdiodrv_work); 399 sdiodrv_dma_shutdown(); 400 } 401 402 void sdiodrv_dma_write_cb(int lch, u16 ch_status, void *data) 403 { 404 sdiodrv_dma_shutdown(); 405 } 406 407 int sdiodrv_dma_init(void) 408 { 409 int rc; 410 411 rc = omap_request_dma(TIWLAN_MMC_DMA_TX, "SDIO WRITE", sdiodrv_dma_write_cb, &g_drv, &g_drv.dma_tx_channel); 412 if (rc != 0) { 413 PERR("sdiodrv_dma_init() omap_request_dma(TIWLAN_MMC_DMA_TX) FAILED\n"); 414 goto out; 415 } 416 417 rc = omap_request_dma(TIWLAN_MMC_DMA_RX, "SDIO READ", sdiodrv_dma_read_cb, &g_drv, &g_drv.dma_rx_channel); 418 if (rc != 0) { 419 PERR("sdiodrv_dma_init() omap_request_dma(TIWLAN_MMC_DMA_RX) FAILED\n"); 420 goto freetx; 421 } 422 423 omap_set_dma_src_params(g_drv.dma_rx_channel, 424 0, // src_port is only for OMAP1 425 OMAP_DMA_AMODE_CONSTANT, 426 (TIWLAN_MMC_CONTROLLER_BASE_ADDR) + OMAP_HSMMC_DATA, 0, 0); 427 428 omap_set_dma_dest_params(g_drv.dma_tx_channel, 429 0, // dest_port is only for OMAP1 430 OMAP_DMA_AMODE_CONSTANT, 431 (TIWLAN_MMC_CONTROLLER_BASE_ADDR) + OMAP_HSMMC_DATA, 0, 0); 432 433 return 0; 434 435 freetx: 436 omap_free_dma(g_drv.dma_tx_channel); 437 out: 438 return rc; 439 } 440 441 static void sdiodrv_dma_shutdown(void) 442 { 443 omap_free_dma(g_drv.dma_tx_channel); 444 omap_free_dma(g_drv.dma_rx_channel); 445 } /* sdiodrv_dma_shutdown() */ 446 447 static u32 sdiodrv_poll_status(u32 reg_offset, u32 stat, unsigned int msecs) 448 { 449 u32 status=0, loops=0; 450 451 do 452 { 453 status = OMAP_HSMMC_READ_OFFSET(reg_offset); 454 if(( status & stat)) 455 { 456 break; 457 } 458 } while (loops++ < SDIODRV_MAX_LOOPS); 459 460 return status; 461 } /* sdiodrv_poll_status */ 462 463 void dumpreg(void) 464 { 465 printk(KERN_ERR "\n MMCHS_SYSCONFIG for mmc3 = %x ", omap_readl( 0x480AD010 )); 466 printk(KERN_ERR "\n MMCHS_SYSSTATUS for mmc3 = %x ", omap_readl( 0x480AD014 )); 467 printk(KERN_ERR "\n MMCHS_CSRE for mmc3 = %x ", omap_readl( 0x480AD024 )); 468 printk(KERN_ERR "\n MMCHS_SYSTEST for mmc3 = %x ", omap_readl( 0x480AD028 )); 469 printk(KERN_ERR "\n MMCHS_CON for mmc3 = %x ", omap_readl( 0x480AD02C )); 470 printk(KERN_ERR "\n MMCHS_PWCNT for mmc3 = %x ", omap_readl( 0x480AD030 )); 471 printk(KERN_ERR "\n MMCHS_BLK for mmc3 = %x ", omap_readl( 0x480AD104 )); 472 printk(KERN_ERR "\n MMCHS_ARG for mmc3 = %x ", omap_readl( 0x480AD108 )); 473 printk(KERN_ERR "\n MMCHS_CMD for mmc3 = %x ", omap_readl( 0x480AD10C )); 474 printk(KERN_ERR "\n MMCHS_RSP10 for mmc3 = %x ", omap_readl( 0x480AD110 )); 475 printk(KERN_ERR "\n MMCHS_RSP32 for mmc3 = %x ", omap_readl( 0x480AD114 )); 476 printk(KERN_ERR "\n MMCHS_RSP54 for mmc3 = %x ", omap_readl( 0x480AD118 )); 477 printk(KERN_ERR "\n MMCHS_RSP76 for mmc3 = %x ", omap_readl( 0x480AD11C )); 478 printk(KERN_ERR "\n MMCHS_DATA for mmc3 = %x ", omap_readl( 0x480AD120 )); 479 printk(KERN_ERR "\n MMCHS_PSTATE for mmc3 = %x ", omap_readl( 0x480AD124 )); 480 printk(KERN_ERR "\n MMCHS_HCTL for mmc3 = %x ", omap_readl( 0x480AD128 )); 481 printk(KERN_ERR "\n MMCHS_SYSCTL for mmc3 = %x ", omap_readl( 0x480AD12C )); 482 printk(KERN_ERR "\n MMCHS_STAT for mmc3 = %x ", omap_readl( 0x480AD130 )); 483 printk(KERN_ERR "\n MMCHS_IE for mmc3 = %x ", omap_readl( 0x480AD134 )); 484 printk(KERN_ERR "\n MMCHS_ISE for mmc3 = %x ", omap_readl( 0x480AD138 )); 485 printk(KERN_ERR "\n MMCHS_AC12 for mmc3 = %x ", omap_readl( 0x480AD13C )); 486 printk(KERN_ERR "\n MMCHS_CAPA for mmc3 = %x ", omap_readl( 0x480AD140 )); 487 printk(KERN_ERR "\n MMCHS_CUR_CAPA for mmc3 = %x ", omap_readl( 0x480AD148 )); 488 } 489 490 //cmd flow p. 3609 obc 491 static int sdiodrv_send_command(u32 cmdreg, u32 cmdarg) 492 { 493 OMAP_HSMMC_WRITE(STAT, OMAP_HSMMC_STAT_CLEAR); 494 OMAP_HSMMC_SEND_COMMAND(cmdreg, cmdarg); 495 496 return sdiodrv_poll_status(OMAP_HSMMC_STAT, CC, MMC_TIMEOUT_MS); 497 } /* sdiodrv_send_command() */ 498 499 /* 500 * Disable clock to the card 501 */ 502 static void OMAP3430_mmc_stop_clock(void) 503 { 504 OMAP_HSMMC_WRITE(SYSCTL, OMAP_HSMMC_READ(SYSCTL) & ~CEN); 505 if ((OMAP_HSMMC_READ(SYSCTL) & CEN) != 0x0) 506 { 507 PERR("MMC clock not stoped, clock freq can not be altered\n"); 508 } 509 } /* OMAP3430_mmc_stop_clock */ 510 511 /* 512 * Reset the SD system 513 */ 514 int OMAP3430_mmc_reset(void) 515 { 516 int status, loops=0; 517 //p. 3598 - need to set SOFTRESET to 0x1 0bc 518 OMAP_HSMMC_WRITE(SYSCTL, OMAP_HSMMC_READ(SYSCTL) | SRA); 519 while ((status = OMAP_HSMMC_READ(SYSCTL) & SRA) && loops++ < SDIODRV_MAX_LOOPS); 520 if (status & SRA) 521 { 522 PERR("OMAP3430_mmc_reset() MMC reset FAILED!! status=0x%x\n",status); 523 } 524 525 return status; 526 527 } /* OMAP3430_mmc_reset */ 528 529 //p. 3611 530 static void OMAP3430_mmc_set_clock(unsigned int clock, OMAP3430_sdiodrv_t *host) 531 { 532 u16 dsor = 0; 533 unsigned long regVal; 534 int status; 535 536 PDEBUG("OMAP3430_mmc_set_clock(%d)\n",clock); 537 if (clock) { 538 /* Enable MMC_SD_CLK */ 539 dsor = OMAP_MMC_MASTER_CLOCK / clock; 540 if (dsor < 1) { 541 dsor = 1; 542 } 543 if (OMAP_MMC_MASTER_CLOCK / dsor > clock) { 544 dsor++; 545 } 546 if (dsor > 250) { 547 dsor = 250; 548 } 549 } 550 OMAP3430_mmc_stop_clock(); 551 regVal = OMAP_HSMMC_READ(SYSCTL); 552 regVal = regVal & ~(CLKD_MASK);//p. 3652 553 regVal = regVal | (dsor << 6); 554 regVal = regVal | (DTO << 16);//data timeout 555 OMAP_HSMMC_WRITE(SYSCTL, regVal); 556 OMAP_HSMMC_WRITE(SYSCTL, OMAP_HSMMC_READ(SYSCTL) | ICE);//internal clock enable. obc not mentioned in the spec 557 /* 558 * wait till the the clock is stable (ICS) bit is set 559 */ 560 status = sdiodrv_poll_status(OMAP_HSMMC_SYSCTL, ICS, MMC_TIMEOUT_MS); 561 if(!(status & ICS)) { 562 PERR("OMAP3430_mmc_set_clock() clock not stable!! status=0x%x\n",status); 563 } 564 /* 565 * Enable clock to the card 566 */ 567 OMAP_HSMMC_WRITE(SYSCTL, OMAP_HSMMC_READ(SYSCTL) | CEN); 568 569 } /* OMAP3430_mmc_set_clock() */ 570 571 static void sdiodrv_free_resources(void) 572 { 573 sdioDrv_cancel_inact_timer(); 574 575 if(g_drv.ifclks_enabled) { 576 sdioDrv_clk_disable(); 577 } 578 579 if (sdiodrv_fclk_got) { 580 clk_put(g_drv.fclk); 581 sdiodrv_fclk_got = 0; 582 } 583 584 if (sdiodrv_iclk_got) { 585 clk_put(g_drv.iclk); 586 sdiodrv_iclk_got = 0; 587 } 588 589 if (sdiodrv_irq_requested) { 590 free_irq(OMAP_MMC_IRQ, &g_drv); 591 sdiodrv_irq_requested = 0; 592 } 593 } 594 595 int sdioDrv_InitHw(void) 596 { 597 int rc; 598 u32 status; 599 #ifdef SDIO_1_BIT /* see also in SdioAdapter.c */ 600 unsigned long clock_rate = 6000000; 601 #else 602 unsigned long clock_rate = 24000000; 603 #endif 604 605 printk(KERN_INFO "TIWLAN SDIO sdioDrv_InitHw()!!"); 606 607 rc = sdioDrv_clk_enable(); 608 if (rc) { 609 PERR("sdioDrv_InitHw : sdioDrv_clk_enable FAILED !!!\n"); 610 goto err; 611 } 612 613 OMAP3430_mmc_reset(); 614 615 //obc - init sequence p. 3600,3617 616 /* 1.8V */ 617 OMAP_HSMMC_WRITE(CAPA, OMAP_HSMMC_READ(CAPA) | VS18); 618 OMAP_HSMMC_WRITE(HCTL, OMAP_HSMMC_READ(HCTL) | SDVS18);//SDVS fits p. 3650 619 /* clock gating */ 620 OMAP_HSMMC_WRITE(SYSCONFIG, OMAP_HSMMC_READ(SYSCONFIG) | AUTOIDLE); 621 622 /* bus power */ 623 OMAP_HSMMC_WRITE(HCTL, OMAP_HSMMC_READ(HCTL) | SDBP);//SDBP fits p. 3650 624 /* interrupts */ 625 OMAP_HSMMC_WRITE(ISE, 0); 626 OMAP_HSMMC_WRITE(IE, IE_EN_MASK); 627 628 //p. 3601 suggests moving to the end 629 OMAP3430_mmc_set_clock(clock_rate, &g_drv); 630 printk("SDIO clock Configuration is now set to %dMhz\n",(int)clock_rate/1000000); 631 632 /* Bus width */ 633 #ifdef SDIO_1_BIT /* see also in SdioAdapter.c */ 634 PDEBUG("%s() setting %d data lines\n",__FUNCTION__, 1); 635 OMAP_HSMMC_WRITE(HCTL, OMAP_HSMMC_READ(HCTL) & (ONE_BIT)); 636 #else 637 PDEBUG("%s() setting %d data lines\n",__FUNCTION__, 4); 638 OMAP_HSMMC_WRITE(HCTL, OMAP_HSMMC_READ(HCTL) | (1 << 1));//DTW 4 bits - p. 3650 639 #endif 640 641 /* send the init sequence. 80 clocks of synchronization in the SDIO */ 642 //doesn't match p. 3601,3617 - obc 643 OMAP_HSMMC_WRITE( CON, OMAP_HSMMC_READ(CON) | INIT_STREAM); 644 OMAP_HSMMC_SEND_COMMAND( 0, 0); 645 status = sdiodrv_poll_status(OMAP_HSMMC_STAT, CC, MMC_TIMEOUT_MS); 646 if (!(status & CC)) { 647 PERR("sdioDrv_InitHw() SDIO Command error status = 0x%x\n", status); 648 rc = status; 649 goto err; 650 } 651 OMAP_HSMMC_WRITE(CON, OMAP_HSMMC_READ(CON) & ~INIT_STREAM); 652 653 return 0; 654 655 err: 656 /* Disabling clocks for now */ 657 sdioDrv_clk_disable(); 658 659 return rc; 660 661 } /* sdiodrv_InitHw */ 662 663 void sdiodrv_shutdown(void) 664 { 665 PDEBUG("entering %s()\n" , __FUNCTION__ ); 666 667 sdiodrv_free_resources(); 668 669 PDEBUG("exiting %s\n", __FUNCTION__); 670 } /* sdiodrv_shutdown() */ 671 672 static int sdiodrv_send_data_xfer_commad(u32 cmd, u32 cmdarg, int length, u32 buffer_enable_status, unsigned int bBlkMode) 673 { 674 int status; 675 676 PDEBUG("%s() writing CMD 0x%x ARG 0x%x\n",__FUNCTION__, cmd, cmdarg); 677 678 /* block mode */ 679 if(bBlkMode) { 680 /* 681 * Bits 31:16 of BLK reg: NBLK Blocks count for current transfer. 682 * in case of Block MOde the lenght is treated here as number of blocks 683 * (and not as a length). 684 * Bits 11:0 of BLK reg: BLEN Transfer Block Size. in case of block mode set that field to block size. 685 */ 686 OMAP_HSMMC_WRITE(BLK, (length << 16) | (g_drv.uBlkSize << 0)); 687 688 /* 689 * In CMD reg: 690 * BCE: Block Count Enable 691 * MSBS: Multi/Single block select 692 */ 693 cmd |= MSBS | BCE ; 694 } else { 695 OMAP_HSMMC_WRITE(BLK, length); 696 } 697 698 status = sdiodrv_send_command(cmd, cmdarg); 699 if(!(status & CC)) { 700 PERR("sdiodrv_send_data_xfer_commad() SDIO Command error! STAT = 0x%x\n", status); 701 return 0; 702 } 703 PDEBUG("%s() length = %d(%dw) BLK = 0x%x\n", 704 __FUNCTION__, length,((length + 3) >> 2), OMAP_HSMMC_READ(BLK)); 705 706 return sdiodrv_poll_status(OMAP_HSMMC_PSTATE, buffer_enable_status, MMC_TIMEOUT_MS); 707 708 } /* sdiodrv_send_data_xfer_commad() */ 709 710 int sdiodrv_data_xfer_sync(u32 cmd, u32 cmdarg, void *data, int length, u32 buffer_enable_status) 711 { 712 u32 buf_start, buf_end, data32; 713 int status; 714 715 status = sdiodrv_send_data_xfer_commad(cmd, cmdarg, length, buffer_enable_status, 0); 716 if(!(status & buffer_enable_status)) 717 { 718 PERR("sdiodrv_data_xfer_sync() buffer disabled! length = %d BLK = 0x%x PSTATE = 0x%x\n", 719 length, OMAP_HSMMC_READ(BLK), status); 720 return -1; 721 } 722 buf_end = (u32)data+(u32)length; 723 724 //obc need to check BRE/BWE every time, see p. 3605 725 /* 726 * Read loop 727 */ 728 if (buffer_enable_status == BRE) 729 { 730 if (((u32)data & 3) == 0) /* 4 bytes aligned */ 731 { 732 for (buf_start = (u32)data; (u32)data < buf_end; data += sizeof(unsigned long)) 733 { 734 *((unsigned long*)(data)) = OMAP_HSMMC_READ(DATA); 735 } 736 } 737 else /* 2 bytes aligned */ 738 { 739 for (buf_start = (u32)data; (u32)data < buf_end; data += sizeof(unsigned long)) 740 { 741 data32 = OMAP_HSMMC_READ(DATA); 742 *((unsigned short *)data) = (unsigned short)data32; 743 *((unsigned short *)data + 1) = (unsigned short)(data32 >> 16); 744 } 745 } 746 } 747 /* 748 * Write loop 749 */ 750 else 751 { 752 if (((u32)data & 3) == 0) /* 4 bytes aligned */ 753 { 754 for (buf_start = (u32)data; (u32)data < buf_end; data += sizeof(unsigned long)) 755 { 756 OMAP_HSMMC_WRITE(DATA,*((unsigned long*)(data))); 757 } 758 } 759 else /* 2 bytes aligned */ 760 { 761 for (buf_start = (u32)data; (u32)data < buf_end; data += sizeof(unsigned long)) 762 { 763 OMAP_HSMMC_WRITE(DATA,*((unsigned short*)data) | *((unsigned short*)data+1) << 16 ); 764 } 765 766 } 767 } 768 status = sdiodrv_poll_status(OMAP_HSMMC_STAT, TC, MMC_TIMEOUT_MS); 769 if(!(status & TC)) 770 { 771 PERR("sdiodrv_data_xfer_sync() transfer error! STAT = 0x%x\n", status); 772 return -1; 773 } 774 775 return 0; 776 777 } /* sdiodrv_data_xfer_sync() */ 778 779 int sdioDrv_ConnectBus (void * fCbFunc, 780 void * hCbArg, 781 unsigned int uBlkSizeShift, 782 unsigned int uSdioThreadPriority) 783 { 784 g_drv.BusTxnCB = fCbFunc; 785 g_drv.BusTxnHandle = hCbArg; 786 g_drv.uBlkSizeShift = uBlkSizeShift; 787 g_drv.uBlkSize = 1 << uBlkSizeShift; 788 789 INIT_WORK(&g_drv.sdiodrv_work, sdiodrv_task); 790 791 return sdioDrv_InitHw (); 792 } 793 794 /*--------------------------------------------------------------------------------------*/ 795 796 int sdioDrv_DisconnectBus (void) 797 { 798 /* Disable clocks to handle driver stop command */ 799 sdioDrv_clk_disable(); 800 return 0; 801 } 802 803 //p.3609 cmd flow 804 int sdioDrv_ExecuteCmd (unsigned int uCmd, 805 unsigned int uArg, 806 unsigned int uRespType, 807 void * pResponse, 808 unsigned int uLen) 809 { 810 unsigned int uCmdReg = 0; 811 unsigned int uStatus = 0; 812 unsigned int uResponse = 0; 813 814 PDEBUG("sdioDrv_ExecuteCmd() starting cmd %02x arg %08x\n", (int)uCmd, (int)uArg); 815 816 sdioDrv_clk_enable(); /* To make sure we have clocks enable */ 817 818 uCmdReg = (uCmd << 24) | (uRespType << 16) ; 819 820 uStatus = sdiodrv_send_command(uCmdReg, uArg); 821 822 if (!(uStatus & CC)) 823 { 824 PERR("sdioDrv_ExecuteCmd() SDIO Command error status = 0x%x\n", uStatus); 825 return -1; 826 } 827 if ((uLen > 0) && (uLen <= 4))/*obc - Len > 4 ? shouldn't read anything ? */ 828 { 829 uResponse = OMAP_HSMMC_READ(RSP10); 830 memcpy (pResponse, (char *)&uResponse, uLen); 831 PDEBUG("sdioDrv_ExecuteCmd() response = 0x%x\n", uResponse); 832 } 833 return 0; 834 } 835 836 /*--------------------------------------------------------------------------------------*/ 837 838 int sdioDrv_ReadSync (unsigned int uFunc, 839 unsigned int uHwAddr, 840 void * pData, 841 unsigned int uLen, 842 unsigned int bIncAddr, 843 unsigned int bMore) 844 { 845 unsigned int uCmdArg; 846 int iStatus; 847 848 // printk(KERN_INFO "in sdioDrv_ReadSync\n"); 849 uCmdArg = SDIO_CMD53_READ(0, uFunc, 0, bIncAddr, uHwAddr, uLen); 850 851 iStatus = sdiodrv_data_xfer_sync(OMAP_HSMMC_CMD53_READ, uCmdArg, pData, uLen, BRE); 852 if (iStatus != 0) { 853 PERR("sdioDrv_ReadSync() FAILED!!\n"); 854 } 855 #ifdef TI_SDIO_DEBUG 856 if (uLen == 1) 857 printk(KERN_INFO "R53: [0x%x](%u) = 0x%x\n", uHwAddr, uLen, (unsigned)(*(char *)pData)); 858 else if (uLen == 2) 859 printk(KERN_INFO "R53: [0x%x](%u) = 0x%x\n", uHwAddr, uLen, (unsigned)(*(short *)pData)); 860 else if (uLen == 4) 861 printk(KERN_INFO "R53: [0x%x](%u) = 0x%x\n", uHwAddr, uLen, (unsigned)(*(long *)pData)); 862 else 863 printk(KERN_INFO "R53: [0x%x](%u)\n", uHwAddr, uLen); 864 #endif 865 return iStatus; 866 } 867 868 /*--------------------------------------------------------------------------------------*/ 869 int sdioDrv_ReadAsync (unsigned int uFunc, 870 unsigned int uHwAddr, 871 void * pData, 872 unsigned int uLen, 873 unsigned int bBlkMode, 874 unsigned int bIncAddr, 875 unsigned int bMore) 876 { 877 int iStatus; 878 unsigned int uCmdArg; 879 unsigned int uNumBlks; 880 unsigned int uDmaBlockCount; 881 unsigned int uNumOfElem; 882 dma_addr_t dma_bus_address; 883 884 #ifdef TI_SDIO_DEBUG 885 printk(KERN_INFO "R53: [0x%x](%u) F[%d]\n", uHwAddr, uLen, uFunc); 886 #endif 887 888 //printk(KERN_INFO "in sdioDrv_ReadAsync\n"); 889 890 if (bBlkMode) 891 { 892 /* For block mode use number of blocks instead of length in bytes */ 893 uNumBlks = uLen >> g_drv.uBlkSizeShift; 894 uDmaBlockCount = uNumBlks; 895 /* due to the DMA config to 32Bit per element (OMAP_DMA_DATA_TYPE_S32) the division is by 4 */ 896 uNumOfElem = g_drv.uBlkSize >> 2; 897 } 898 else 899 { 900 uNumBlks = uLen; 901 uDmaBlockCount = 1; 902 uNumOfElem = (uLen + 3) >> 2; 903 } 904 905 uCmdArg = SDIO_CMD53_READ(0, uFunc, bBlkMode, bIncAddr, uHwAddr, uNumBlks); 906 907 iStatus = sdiodrv_send_data_xfer_commad(OMAP_HSMMC_CMD53_READ_DMA, uCmdArg, uNumBlks, BRE, bBlkMode); 908 909 if (!(iStatus & BRE)) 910 { 911 PERR("sdioDrv_ReadAsync() buffer disabled! length = %d BLK = 0x%x PSTATE = 0x%x, BlkMode = %d\n", 912 uLen, OMAP_HSMMC_READ(BLK), iStatus, bBlkMode); 913 goto err; 914 } 915 916 sdiodrv_dma_init(); 917 918 PDEBUG("sdiodrv_read_async() dma_ch=%d \n",g_drv.dma_rx_channel); 919 920 dma_bus_address = dma_map_single(g_drv.dev, pData, uLen, DMA_FROM_DEVICE); 921 if (!dma_bus_address) { 922 PERR("sdioDrv_ReadAsync: dma_map_single failed\n"); 923 goto err; 924 } 925 926 if (g_drv.dma_read_addr != 0) { 927 printk(KERN_ERR "sdioDrv_ReadAsync: previous DMA op is not finished!\n"); 928 BUG(); 929 } 930 931 g_drv.dma_read_addr = dma_bus_address; 932 g_drv.dma_read_size = uLen; 933 934 omap_set_dma_dest_params (g_drv.dma_rx_channel, 935 0, // dest_port is only for OMAP1 936 OMAP_DMA_AMODE_POST_INC, 937 dma_bus_address, 938 0, 0); 939 940 omap_set_dma_transfer_params(g_drv.dma_rx_channel, OMAP_DMA_DATA_TYPE_S32, uNumOfElem , uDmaBlockCount , OMAP_DMA_SYNC_FRAME, TIWLAN_MMC_DMA_RX, OMAP_DMA_SRC_SYNC); 941 942 omap_start_dma(g_drv.dma_rx_channel); 943 944 /* Continued at sdiodrv_irq() after DMA transfer is finished */ 945 #ifdef TI_SDIO_DEBUG 946 printk(KERN_INFO "R53: [0x%x](%u) (A)\n", uHwAddr, uLen); 947 #endif 948 return 0; 949 err: 950 return -1; 951 952 } 953 954 955 /*--------------------------------------------------------------------------------------*/ 956 957 int sdioDrv_WriteSync (unsigned int uFunc, 958 unsigned int uHwAddr, 959 void * pData, 960 unsigned int uLen, 961 unsigned int bIncAddr, 962 unsigned int bMore) 963 { 964 unsigned int uCmdArg; 965 int iStatus; 966 967 // printk(KERN_INFO "in sdioDrv_WriteSync\n"); 968 969 uCmdArg = SDIO_CMD53_WRITE(1, uFunc, 0, bIncAddr, uHwAddr, uLen); 970 971 iStatus = sdiodrv_data_xfer_sync(OMAP_HSMMC_CMD53_WRITE, uCmdArg, pData, uLen, BWE); 972 if (iStatus != 0) 973 { 974 PERR("sdioDrv_WriteSync() FAILED!!\n"); 975 } 976 #ifdef TI_SDIO_DEBUG 977 if (uLen == 1) 978 printk(KERN_INFO "W53: [0x%x](%u) < 0x%x\n", uHwAddr, uLen, (unsigned)(*(char *)pData)); 979 else if (uLen == 2) 980 printk(KERN_INFO "W53: [0x%x](%u) < 0x%x\n", uHwAddr, uLen, (unsigned)(*(short *)pData)); 981 else if (uLen == 4) 982 printk(KERN_INFO "W53: [0x%x](%u) < 0x%x\n", uHwAddr, uLen, (unsigned)(*(long *)pData)); 983 else 984 printk(KERN_INFO "W53: [0x%x](%u)\n", uHwAddr, uLen); 985 #endif 986 return iStatus; 987 } 988 989 /*--------------------------------------------------------------------------------------*/ 990 int sdioDrv_WriteAsync (unsigned int uFunc, 991 unsigned int uHwAddr, 992 void * pData, 993 unsigned int uLen, 994 unsigned int bBlkMode, 995 unsigned int bIncAddr, 996 unsigned int bMore) 997 { 998 int iStatus; 999 unsigned int uCmdArg; 1000 unsigned int uNumBlks; 1001 unsigned int uDmaBlockCount; 1002 unsigned int uNumOfElem; 1003 dma_addr_t dma_bus_address; 1004 1005 #ifdef TI_SDIO_DEBUG 1006 printk(KERN_INFO "W53: [0x%x](%u) F[%d] B[%d] I[%d]\n", uHwAddr, uLen, uFunc, bBlkMode, bIncAddr); 1007 #endif 1008 1009 // printk(KERN_INFO "in sdioDrv_WriteAsync\n"); 1010 if (bBlkMode) 1011 { 1012 /* For block mode use number of blocks instead of length in bytes */ 1013 uNumBlks = uLen >> g_drv.uBlkSizeShift; 1014 uDmaBlockCount = uNumBlks; 1015 /* due to the DMA config to 32Bit per element (OMAP_DMA_DATA_TYPE_S32) the division is by 4 */ 1016 uNumOfElem = g_drv.uBlkSize >> 2; 1017 } 1018 else 1019 { 1020 uNumBlks = uLen; 1021 uDmaBlockCount = 1; 1022 uNumOfElem = (uLen + 3) >> 2; 1023 } 1024 1025 uCmdArg = SDIO_CMD53_WRITE(1, uFunc, bBlkMode, bIncAddr, uHwAddr, uNumBlks); 1026 1027 iStatus = sdiodrv_send_data_xfer_commad(OMAP_HSMMC_CMD53_WRITE_DMA, uCmdArg, uNumBlks, BWE, bBlkMode); 1028 if (!(iStatus & BWE)) 1029 { 1030 PERR("sdioDrv_WriteAsync() buffer disabled! length = %d, BLK = 0x%x, Status = 0x%x\n", 1031 uLen, OMAP_HSMMC_READ(BLK), iStatus); 1032 goto err; 1033 } 1034 1035 OMAP_HSMMC_WRITE(ISE, TC); 1036 1037 sdiodrv_dma_init(); 1038 1039 dma_bus_address = dma_map_single(g_drv.dev, pData, uLen, DMA_TO_DEVICE); 1040 if (!dma_bus_address) { 1041 PERR("sdioDrv_WriteAsync: dma_map_single failed\n"); 1042 goto err; 1043 } 1044 1045 if (g_drv.dma_write_addr != 0) { 1046 PERR("sdioDrv_WriteAsync: previous DMA op is not finished!\n"); 1047 BUG(); 1048 } 1049 1050 g_drv.dma_write_addr = dma_bus_address; 1051 g_drv.dma_write_size = uLen; 1052 1053 omap_set_dma_src_params (g_drv.dma_tx_channel, 1054 0, // src_port is only for OMAP1 1055 OMAP_DMA_AMODE_POST_INC, 1056 dma_bus_address, 1057 0, 0); 1058 1059 omap_set_dma_transfer_params(g_drv.dma_tx_channel, OMAP_DMA_DATA_TYPE_S32, uNumOfElem, uDmaBlockCount, OMAP_DMA_SYNC_FRAME, TIWLAN_MMC_DMA_TX, OMAP_DMA_DST_SYNC); 1060 1061 omap_start_dma(g_drv.dma_tx_channel); 1062 1063 /* Continued at sdiodrv_irq() after DMA transfer is finished */ 1064 return 0; 1065 err: 1066 return -1; 1067 } 1068 1069 /*--------------------------------------------------------------------------------------*/ 1070 1071 int sdioDrv_ReadSyncBytes (unsigned int uFunc, 1072 unsigned int uHwAddr, 1073 unsigned char *pData, 1074 unsigned int uLen, 1075 unsigned int bMore) 1076 { 1077 unsigned int uCmdArg; 1078 unsigned int i; 1079 int iStatus; 1080 1081 for (i = 0; i < uLen; i++) { 1082 uCmdArg = SDIO_CMD52_READ(0, uFunc, 0, uHwAddr); 1083 1084 iStatus = sdiodrv_send_command(OMAP_HSMMC_CMD52_READ, uCmdArg); 1085 1086 if (!(iStatus & CC)) { 1087 PERR("sdioDrv_ReadSyncBytes() SDIO Command error status = 0x%x\n", iStatus); 1088 return -1; 1089 } 1090 else { 1091 *pData = (unsigned char)(OMAP_HSMMC_READ(RSP10)); 1092 } 1093 #ifdef TI_SDIO_DEBUG 1094 printk(KERN_INFO "R52: [0x%x](%u) = 0x%x\n", uHwAddr, uLen, (unsigned)*pData); 1095 #endif 1096 uHwAddr++; 1097 pData++; 1098 } 1099 1100 return 0; 1101 } 1102 1103 /*--------------------------------------------------------------------------------------*/ 1104 1105 int sdioDrv_WriteSyncBytes (unsigned int uFunc, 1106 unsigned int uHwAddr, 1107 unsigned char *pData, 1108 unsigned int uLen, 1109 unsigned int bMore) 1110 { 1111 unsigned int uCmdArg; 1112 unsigned int i; 1113 int iStatus; 1114 1115 for (i = 0; i < uLen; i++) { 1116 #ifdef TI_SDIO_DEBUG 1117 printk(KERN_INFO "W52: [0x%x](%u) < 0x%x\n", uHwAddr, uLen, (unsigned)*pData); 1118 #endif 1119 uCmdArg = SDIO_CMD52_WRITE(1, uFunc, 0, uHwAddr, *pData); 1120 1121 iStatus = sdiodrv_send_command(OMAP_HSMMC_CMD52_WRITE, uCmdArg); 1122 if (!(iStatus & CC)) { 1123 PERR("sdioDrv_WriteSyncBytes() SDIO Command error status = 0x%x\n", iStatus); 1124 return -1; 1125 } 1126 uHwAddr++; 1127 pData++; 1128 } 1129 1130 return 0; 1131 } 1132 1133 static int sdioDrv_probe(struct platform_device *pdev) 1134 { 1135 int rc; 1136 1137 printk(KERN_INFO "TIWLAN SDIO probe: initializing mmc%d device\n", pdev->id + 1); 1138 1139 /* remember device struct for future DMA operations */ 1140 g_drv.dev = &pdev->dev; 1141 g_drv.irq = platform_get_irq(pdev, 0); 1142 if (g_drv.irq < 0) 1143 return -ENXIO; 1144 1145 rc= request_irq(OMAP_MMC_IRQ, sdiodrv_irq, 0, SDIO_DRIVER_NAME, &g_drv); 1146 if (rc != 0) { 1147 PERR("sdioDrv_probe() - request_irq FAILED!!\n"); 1148 return rc; 1149 } 1150 sdiodrv_irq_requested = 1; 1151 1152 spin_lock_init(&g_drv.clk_lock); 1153 1154 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 31)) 1155 dummy_pdev.id = TIWLAN_MMC_CONTROLLER; 1156 dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%lu", TIWLAN_MMC_CONTROLLER); 1157 g_drv.fclk = clk_get(&dummy_pdev.dev, "fck"); 1158 #else 1159 g_drv.fclk = clk_get(&pdev->dev, "mmchs_fck"); 1160 #endif 1161 if (IS_ERR(g_drv.fclk)) { 1162 rc = PTR_ERR(g_drv.fclk); 1163 PERR("clk_get(fclk) FAILED !!!\n"); 1164 goto err; 1165 } 1166 sdiodrv_fclk_got = 1; 1167 1168 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 31)) 1169 g_drv.iclk = clk_get(&dummy_pdev.dev, "ick"); 1170 #else 1171 g_drv.iclk = clk_get(&pdev->dev, "mmchs_ick"); 1172 #endif 1173 if (IS_ERR(g_drv.iclk)) { 1174 rc = PTR_ERR(g_drv.iclk); 1175 PERR("clk_get(iclk) FAILED !!!\n"); 1176 goto err; 1177 } 1178 sdiodrv_iclk_got = 1; 1179 1180 printk("Configuring SDIO DMA registers!!!\n"); 1181 printk("pdev->id is %d!!!\n", pdev->id); 1182 if ( pdev->id == 1 ) { 1183 /* MMC2 */ 1184 TIWLAN_MMC_CONTROLLER_BASE_ADDR = OMAP_HSMMC2_BASE; 1185 TIWLAN_MMC_DMA_TX = OMAP24XX_DMA_MMC2_TX; 1186 TIWLAN_MMC_DMA_RX = OMAP24XX_DMA_MMC2_RX; 1187 } 1188 else if ( pdev->id == 2 ) { 1189 /* MMC3 */ 1190 TIWLAN_MMC_CONTROLLER_BASE_ADDR = OMAP_HSMMC3_BASE; 1191 TIWLAN_MMC_DMA_TX = OMAP34XX_DMA_MMC3_TX; 1192 TIWLAN_MMC_DMA_RX = OMAP34XX_DMA_MMC3_RX; 1193 } 1194 1195 /* inactivity timer initialization*/ 1196 init_timer(&g_drv.inact_timer); 1197 g_drv.inact_timer.function = sdioDrv_inact_timer; 1198 g_drv.inact_timer_running = 0; 1199 1200 return 0; 1201 err: 1202 sdiodrv_free_resources(); 1203 return rc; 1204 } 1205 1206 static int sdioDrv_remove(struct platform_device *pdev) 1207 { 1208 printk(KERN_INFO "sdioDrv_remove: calling sdiodrv_shutdown\n"); 1209 1210 sdiodrv_shutdown(); 1211 1212 return 0; 1213 } 1214 1215 #ifdef CONFIG_PM 1216 static int sdioDrv_suspend(struct platform_device *pdev, pm_message_t state) 1217 { 1218 printk(KERN_INFO "TISDIO: sdioDrv is suspending\n"); 1219 return 0; 1220 } 1221 1222 /* Routine to resume the MMC device */ 1223 static int sdioDrv_resume(struct platform_device *pdev) 1224 { 1225 printk(KERN_INFO "TISDIO: sdioDrv is resuming\n"); 1226 return 0; 1227 } 1228 #else 1229 #define sdioDrv_suspend NULL 1230 #define sdioDrv_resume NULL 1231 #endif 1232 1233 static struct platform_driver sdioDrv_struct = { 1234 .probe = sdioDrv_probe, 1235 .remove = sdioDrv_remove, 1236 .suspend = sdioDrv_suspend, 1237 .resume = sdioDrv_resume, 1238 .driver = { 1239 .name = SDIO_DRIVER_NAME, 1240 }, 1241 }; 1242 1243 void sdioDrv_register_pm(int (*wlanDrvIf_Start)(void), 1244 int (*wlanDrvIf_Stop)(void)) 1245 { 1246 g_drv.wlanDrvIf_pm_resume = wlanDrvIf_Start; 1247 g_drv.wlanDrvIf_pm_suspend = wlanDrvIf_Stop; 1248 } 1249 1250 int sdioDrv_clk_enable(void) 1251 { 1252 unsigned long flags; 1253 int ret = 0; 1254 1255 spin_lock_irqsave(&g_drv.clk_lock, flags); 1256 if (g_drv.ifclks_enabled) 1257 goto done; 1258 1259 ret = clk_enable(g_drv.iclk); 1260 if (ret) 1261 goto clk_en_err1; 1262 1263 ret = clk_enable(g_drv.fclk); 1264 if (ret) 1265 goto clk_en_err2; 1266 g_drv.ifclks_enabled = 1; 1267 1268 sdioDrv_hsmmc_restore_ctx(); 1269 1270 done: 1271 spin_unlock_irqrestore(&g_drv.clk_lock, flags); 1272 return ret; 1273 1274 clk_en_err2: 1275 clk_disable(g_drv.iclk); 1276 clk_en_err1 : 1277 spin_unlock_irqrestore(&g_drv.clk_lock, flags); 1278 return ret; 1279 } 1280 1281 void sdioDrv_clk_disable(void) 1282 { 1283 unsigned long flags; 1284 1285 spin_lock_irqsave(&g_drv.clk_lock, flags); 1286 if (!g_drv.ifclks_enabled) 1287 goto done; 1288 1289 sdioDrv_hsmmc_save_ctx(); 1290 1291 clk_disable(g_drv.fclk); 1292 clk_disable(g_drv.iclk); 1293 g_drv.ifclks_enabled = 0; 1294 done: 1295 spin_unlock_irqrestore(&g_drv.clk_lock, flags); 1296 } 1297 1298 #ifdef TI_SDIO_STANDALONE 1299 static int __init sdioDrv_init(void) 1300 #else 1301 int __init sdioDrv_init(int sdcnum) 1302 #endif 1303 { 1304 memset(&g_drv, 0, sizeof(g_drv)); 1305 memset(&hsmmc_ctx, 0, sizeof(hsmmc_ctx)); 1306 1307 printk(KERN_INFO "TIWLAN SDIO init\n"); 1308 #ifndef TI_SDIO_STANDALONE 1309 sdio_init( sdcnum ); 1310 #endif 1311 g_drv.sdio_wq = create_freezeable_workqueue(SDIOWQ_NAME); 1312 if (!g_drv.sdio_wq) { 1313 printk("TISDIO: Fail to create SDIO WQ\n"); 1314 return -EINVAL; 1315 } 1316 /* Register the sdio driver */ 1317 return platform_driver_register(&sdioDrv_struct); 1318 } 1319 1320 #ifdef TI_SDIO_STANDALONE 1321 static 1322 #endif 1323 void __exit sdioDrv_exit(void) 1324 { 1325 /* Unregister sdio driver */ 1326 platform_driver_unregister(&sdioDrv_struct); 1327 if (g_drv.sdio_wq) 1328 destroy_workqueue(g_drv.sdio_wq); 1329 } 1330 1331 #ifdef TI_SDIO_STANDALONE 1332 module_init(sdioDrv_init); 1333 module_exit(sdioDrv_exit); 1334 #endif 1335 1336 EXPORT_SYMBOL(sdioDrv_ConnectBus); 1337 EXPORT_SYMBOL(sdioDrv_DisconnectBus); 1338 EXPORT_SYMBOL(sdioDrv_ExecuteCmd); 1339 EXPORT_SYMBOL(sdioDrv_ReadSync); 1340 EXPORT_SYMBOL(sdioDrv_WriteSync); 1341 EXPORT_SYMBOL(sdioDrv_ReadAsync); 1342 EXPORT_SYMBOL(sdioDrv_WriteAsync); 1343 EXPORT_SYMBOL(sdioDrv_ReadSyncBytes); 1344 EXPORT_SYMBOL(sdioDrv_WriteSyncBytes); 1345 EXPORT_SYMBOL(sdioDrv_register_pm); 1346 MODULE_DESCRIPTION("TI WLAN SDIO driver"); 1347 MODULE_LICENSE("GPL"); 1348 MODULE_ALIAS(SDIO_DRIVER_NAME); 1349 MODULE_AUTHOR("Texas Instruments Inc"); 1350 #endif 1351
