| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 89 BuildMI(*MBB, MII, MI->getDebugLoc(),
92 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr),
95 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
97 BuildMI(*MBB, MII, MI->getDebugLoc(),
102 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri),
104 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
106 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::STriw))
112 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
114 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::STriw)).
131 BuildMI(*MBB, MII, MI->getDebugLoc()
[all...] |
| HexagonSplitTFRCondSets.cpp | 94 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_cPt),
98 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_cNotPt),
108 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFRI_cPt),
110 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFRI_cNotPt),
|
| HexagonRegisterInfo.cpp | 193 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
195 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
199 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
219 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
221 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
225 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
239 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
241 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
247 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
255 BuildMI(*MI.getParent(), II, MI.getDebugLoc()
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcFrameLowering.cpp | 55 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVEri), SP::O6)
61 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
63 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
65 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVErr), SP::O6)
78 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
|
| SparcInstrInfo.cpp | 121 MachineInstrBuilder MIB = BuildMI(MF, dl, get(SP::DBG_VALUE))
205 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
207 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA))
240 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
248 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
250 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
254 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
285 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
288 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
291 BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD), DestReg
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUFrameLowering.cpp | 120 BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL)).addSym(FrameLabel);
125 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16)
129 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
132 BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
137 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2)
140 BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2)
142 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQXr32), SPU::R1)
145 BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1)
148 BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2)
151 BuildMI(MBB, MBBI, dl, TII.get(SPU::LQXr128), SPU::R2
[all...] |
| SPUNopFiller.cpp | 96 BuildMI(MBB, I, I->getDebugLoc(), TII->get(SPU::ENOP));
105 BuildMI(MBB, I, I->getDebugLoc(), TII->get(SPU::LNOP));
121 BuildMI(MBB, J, J->getDebugLoc(), TII->get(SPU::ENOP));
126 BuildMI(MBB, J, DebugLoc(), TII->get(SPU::LNOP));
|
| SPUInstrInfo.cpp | 134 BuildMI(MBB, I, DL, get(SPU::LRr128), DestReg)
169 addFrameReference(BuildMI(MBB, MI, DL, get(opc))
204 addFrameReference(BuildMI(MBB, MI, DL, get(opc), DestReg), FrameIdx);
368 MIB = BuildMI(&MBB, DL, get(SPU::HBR_LABEL)).addSym(branchLabel);
374 MIB = BuildMI(&MBB, DL, get(SPU::BR));
382 MIB = BuildMI( MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
388 MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
392 MIB = BuildMI(MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
402 MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
403 MachineInstrBuilder MIB2 = BuildMI(&MBB, DL, get(SPU::BR))
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 10 // This file exposes a function named BuildMI, which is useful for dramatically
13 // M = BuildMI(X86::ADDrr8, 2).addReg(argVal1).addReg(argVal2);
184 /// BuildMI - Builder interface. Specify how to create the initial instruction
187 inline MachineInstrBuilder BuildMI(MachineFunction &MF,
193 /// BuildMI - This version of the builder sets up the first operand as a
196 inline MachineInstrBuilder BuildMI(MachineFunction &MF,
204 /// BuildMI - This version of the builder inserts the newly-built
208 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
218 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
228 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 136 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
140 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
145 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
149 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
154 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
158 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
162 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
315 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0);
318 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
324 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)
[all...] |
| PPCInstrInfo.cpp | 160 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
184 BuildMI(MBB, MI, DL, get(PPC::NOP));
307 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
309 BuildMI(&MBB, DL, get(PPC::BCC))
315 BuildMI(&MBB, DL, get(PPC::BCC))
317 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
343 BuildMI(MBB, I, DL, MCID, DestReg)
346 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
359 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
367 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11))
[all...] |
| PPCRegisterInfo.cpp | 218 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
223 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
225 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
228 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
302 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
307 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
311 BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0)
315 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
324 BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
329 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 134 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
139 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
225 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
230 BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
236 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
246 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
251 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
257 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
275 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
280 BuildMI(MBB, II, dl, TII.get(NewOpcode)
[all...] |
| XCoreInstrInfo.cpp | 287 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
291 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
300 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
302 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
342 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
349 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
354 BuildMI(MBB, I, DL, get(XCore::SETSP_1r))
370 BuildMI(MBB, I, DL, get(XCore::STWFI))
384 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
393 MachineInstrBuilder MIB = BuildMI(MF, DL, get(XCore::DBG_VALUE)
[all...] |
| XCoreFrameLowering.cpp | 55 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
70 BuildMI(MBB, I, dl, TII.get(Opcode))
135 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
142 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel);
161 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveLRLabel);
177 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveR10Label);
184 BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr)
189 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel);
225 BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r))
264 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 66 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW)
98 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW)
135 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW);
156 BuildMI(MBB, MBBI, DL,
160 BuildMI(MBB, MBBI, DL,
170 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW)
199 BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r))
220 BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), CSI[i].getReg());
|
| MSP430InstrInfo.cpp | 51 BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
55 BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
79 BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
82 BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
100 BuildMI(MBB, I, DL, get(Opc), DestReg)
272 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
278 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
283 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
|
| /external/llvm/lib/Target/Mips/ |
| MipsExpandPseudo.cpp | 72 BuildMI(MBB, I, I->getDebugLoc(), TII->get(Mips::ADDu),
103 BuildMI(MBB, I, dl, Mtc1Tdd, *SubReg).addReg(LoReg);
104 BuildMI(MBB, I, dl, Mtc1Tdd, *(SubReg + 1)).addReg(HiReg);
116 BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(*(SubReg + N));
|
| MipsEmitGPRestore.cpp | 70 BuildMI(MBB, I, dl, TII->get(Mips::LW), Mips::GP).addFrameIndex(FI)
83 BuildMI(MBB, ++I, dl, TII->get(Mips::LW), Mips::GP).addFrameIndex(FI)
|
| MipsFrameLowering.cpp | 115 BuildMI(MBB, II, DL, TII.get(LUi), ATReg)
118 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg)
123 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg)
126 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(Reg).addReg(ATReg);
172 BuildMI(*NewEntry, NewEntry->begin(), dl, TII.get(Mips:: SETGP01),
185 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(-StackSize);
193 BuildMI(MBB, MBBI, dl,
210 BuildMI(MBB, MBBI, dl,
245 BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO);
249 BuildMI(MBB, MBBI, dl
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeFrameLowering.cpp | 255 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), r)
263 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R17)
266 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R18)
272 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::MFS), MBlaze::R11)
274 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R11)
277 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R11)
279 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::MTS), MBlaze::RMSR)
284 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R18)
287 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R17)
293 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), r
[all...] |
| MBlazeInstrInfo.cpp | 80 BuildMI(MBB, MI, DL, get(MBlaze::NOP));
88 llvm::BuildMI(MBB, I, DL, get(MBlaze::ADDK), DestReg)
98 BuildMI(MBB, I, DL, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill))
108 BuildMI(MBB, I, DL, get(MBlaze::LWI), DestReg)
202 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
204 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
208 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
209 BuildMI(&MBB, DL, get(MBlaze::BRID)).addMBB(FBB);
291 BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
|
| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 45 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
73 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi))
101 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
|
| Thumb2RegisterInfo.cpp | 48 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
|
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
693 BuildMI(MBB, MBBI, DL,
735 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
742 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
763 BuildMI(MBB, MBBI, DL,
771 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
788 BuildMI(MBB, MBBI, DL,
815 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label)
[all...] |
