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    Searched refs:DefReg (Results 1 - 8 of 8) sorted by null

  /external/llvm/lib/CodeGen/
TargetInstrInfoImpl.cpp 396 unsigned DefReg = MI->getOperand(0).getReg();
402 if (TargetRegisterInfo::isVirtualRegister(DefReg) &&
403 MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg))
454 if (MO.isDef() && Reg != DefReg)
TailDuplication.cpp 383 unsigned DefReg = MI->getOperand(0).getReg();
387 const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
388 LocalVRMap.insert(std::make_pair(DefReg, SrcReg));
394 if (isDefLiveOut(DefReg, TailBB, MRI) || RegsUsedByPhi.count(DefReg))
395 AddSSAUpdateEntry(DefReg, NewDef, PredBB);
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PHIElimination.cpp 139 unsigned DefReg = DefMI->getOperand(0).getReg();
140 if (MRI->use_nodbg_empty(DefReg))
LiveVariables.cpp 216 unsigned DefReg = MO.getReg();
217 if (TRI->isSubRegister(Reg, DefReg)) {
218 PartDefRegs.insert(DefReg);
219 for (const uint16_t *SubRegs = TRI->getSubRegisters(DefReg);
TwoAddressInstructionPass.cpp 205 unsigned DefReg = 0;
222 if (DefReg)
225 DefReg = MO.getReg();
273 if (DefReg == MOReg)
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MachineVerifier.cpp 768 unsigned DefReg = MI->getOperand(defIdx).getReg();
769 if (Reg == DefReg)
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  /external/llvm/lib/Target/Hexagon/
HexagonHardwareLoops.cpp 281 unsigned DefReg = MPhi->getOperand(0).getReg();
288 if (isInductionOperation(DI, DefReg)) {
  /external/llvm/lib/Target/ARM/
ARMLoadStoreOptimizer.cpp 406 unsigned DefReg = MO->getReg();
407 if (std::find(ImpDefs.begin(), ImpDefs.end(), DefReg) == ImpDefs.end())
408 ImpDefs.push_back(DefReg);
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