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    Searched refs:ImplicitDefs (Results 1 - 11 of 11) sorted by null

  /external/llvm/include/llvm/MC/
MCInstrDesc.h 143 const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr
475 return ImplicitDefs;
481 if (ImplicitDefs == 0) return 0;
483 for (; ImplicitDefs[i]; ++i) /*empty*/;
499 if (const uint16_t *ImpDefs = ImplicitDefs)
  /external/llvm/lib/CodeGen/SelectionDAG/
FastISel.cpp     [all...]
ScheduleDAGFast.cpp 426 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
509 if (!MCID.ImplicitDefs)
ScheduleDAGSDNodes.cpp 125 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
ScheduleDAGRRList.cpp     [all...]
  /external/llvm/utils/TableGen/
CodeGenInstruction.cpp 322 ImplicitDefs = R->getValueAsListOfDefs("Defs");
340 if (ImplicitDefs.empty()) return MVT::Other;
343 Record *FirstImplicitDef = ImplicitDefs[0];
CodeGenInstruction.h 214 /// ImplicitDefs/ImplicitUses - These are lists of registers that are
216 std::vector<Record*> ImplicitDefs, ImplicitUses;
DAGISelMatcherGen.cpp 782 HandledReg = II.ImplicitDefs[0];
    [all...]
CodeGenDAGPatterns.cpp     [all...]
  /external/llvm/lib/Target/ARM/
ARMFastISel.cpp 311 .addReg(II.ImplicitDefs[0]));
333 .addReg(II.ImplicitDefs[0]));
358 .addReg(II.ImplicitDefs[0]));
380 .addReg(II.ImplicitDefs[0]));
402 .addReg(II.ImplicitDefs[0]));
427 .addReg(II.ImplicitDefs[0]));
446 .addReg(II.ImplicitDefs[0]));
466 .addReg(II.ImplicitDefs[0]));
    [all...]
  /external/llvm/lib/CodeGen/
MachineInstr.cpp 493 if (MCID->ImplicitDefs)
    [all...]

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