| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 302 static bool isValidIndexedLoad(const LoadSDNode *LD) {
330 LoadSDNode *LD = cast<LoadSDNode>(N);
359 LoadSDNode *LD = cast<LoadSDNode>(N1);
|
| MSP430ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 78 SDNode *SelectBaseOffsetLoad(LoadSDNode *LD, DebugLoc dl);
79 SDNode *SelectIndexedLoad(LoadSDNode *LD, DebugLoc dl);
80 SDNode *SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode,
82 SDNode *SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode,
297 SDNode *HexagonDAGToDAGISel::SelectBaseOffsetLoad(LoadSDNode *LD, DebugLoc dl) {
343 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
407 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
484 SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, DebugLoc dl) {
580 LoadSDNode *LD = cast<LoadSDNode>(N)
[all...] |
| HexagonISelLowering.cpp | 633 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGNodes.h | [all...] |
| SelectionDAG.h | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 130 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
299 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
|
| DAGCombiner.cpp | 721 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
[all...] |
| LegalizeTypes.h | 240 SDValue PromoteIntRes_LOAD(LoadSDNode *N);
314 void ExpandIntRes_LOAD (LoadSDNode *N, SDValue &Lo, SDValue &Hi);
521 SDValue ScalarizeVecRes_LOAD(LoadSDNode *N);
566 void SplitVecRes_LOAD(LoadSDNode *N, SDValue &Lo, SDValue &Hi);
650 LoadSDNode *LD);
658 LoadSDNode *LD, ISD::LoadExtType ExtType);
[all...] |
| SelectionDAGDumper.cpp | 437 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) {
|
| SelectionDAG.cpp | 424 const LoadSDNode *LD = cast<LoadSDNode>(N);
[all...] |
| LegalizeTypesGeneric.cpp | 206 LoadSDNode *LD = cast<LoadSDNode>(N);
|
| LegalizeVectorTypes.cpp | 58 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
185 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
468 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
738 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
[all...] |
| LegalizeFloatTypes.cpp | 473 LoadSDNode *L = cast<LoadSDNode>(N);
[all...] |
| TargetLowering.cpp | [all...] |
| LegalizeDAG.cpp | 415 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
[all...] |
| LegalizeIntegerTypes.cpp | 66 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
413 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 195 bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
400 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
584 bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 729 ? cast<LoadSDNode>(Op)->getAddressingMode()
765 ? cast<LoadSDNode>(Op)->getAddressingMode()
785 ? cast<LoadSDNode>(Op)->getAddressingMode()
858 ? cast<LoadSDNode>(Op)->getAddressingMode()
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 401 LoadSDNode *LD = cast<LoadSDNode>(Op);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | [all...] |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 559 LoadSDNode *LN = cast<LoadSDNode>(Op);
[all...] |
