| /external/llvm/include/llvm/Target/ |
| TargetSelectionDAGInfo.h | 59 SDValue Op1, SDValue Op2,
76 SDValue Op1, SDValue Op2,
92 SDValue Op1, SDValue Op2,
|
| /system/core/libpixelflinger/codeflinger/ |
| ARMAssemblerInterface.h | 116 uint32_t Op2) = 0;
216 ADC(int cc, int s, int Rd, int Rn, uint32_t Op2) {
217 dataProcessing(opADC, cc, s, Rd, Rn, Op2);
220 ADD(int cc, int s, int Rd, int Rn, uint32_t Op2) {
221 dataProcessing(opADD, cc, s, Rd, Rn, Op2);
224 AND(int cc, int s, int Rd, int Rn, uint32_t Op2) {
225 dataProcessing(opAND, cc, s, Rd, Rn, Op2);
228 BIC(int cc, int s, int Rd, int Rn, uint32_t Op2) {
229 dataProcessing(opBIC, cc, s, Rd, Rn, Op2);
232 EOR(int cc, int s, int Rd, int Rn, uint32_t Op2) {
[all...] |
| ARMAssembler.h | 62 uint32_t Op2);
|
| ARMAssemblerProxy.h | 52 uint32_t Op2);
|
| ARMAssemblerProxy.cpp | 70 int Rd, int Rn, uint32_t Op2)
72 mTarget->dataProcessing(opcode, cc, s, Rd, Rn, Op2);
|
| ARMAssembler.cpp | 212 int s, int Rd, int Rn, uint32_t Op2)
214 *mPC++ = (cc<<28) | (opcode<<21) | (s<<20) | (Rn<<16) | (Rd<<12) | Op2;
|
| /external/llvm/lib/Target/PTX/ |
| PTXSelectionDAGInfo.h | 44 SDValue Op1, SDValue Op2,
|
| PTXInstrInfo.h | 121 SDValue Op1, SDValue Op2);
|
| PTXInstrInfo.cpp | 327 DebugLoc dl, EVT VT, SDValue Op1, SDValue Op2) {
330 SDValue ops[] = { Op1, Op2, predReg, predOp };
|
| PTXISelLowering.cpp | 158 SDValue Op2 = Op.getOperand(2);
182 return DAG.getNode(ISD::SETCC, dl, MVT::i1, Op0, Op1, Op2);
|
| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 60 SDValue Op1, SDValue Op2,
|
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAG.h | 487 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
493 Ops.push_back(Op2);
712 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2);
713 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
715 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
717 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
729 SDValue Op1, SDValue Op2);
731 SDValue Op1, SDValue Op2, SDValue Op3);
[all...] |
| ISDOpcodes.h | [all...] |
| FastISel.h | 267 unsigned Op2, bool Op2IsKill);
|
| /external/llvm/lib/Target/PTX/InstPrinter/ |
| PTXInstPrinter.cpp | 201 const MCOperand &Op2 = MI->getOperand(OpNo+1);
203 if (Op2.getImm() == 0)
205 O << "+" << Op2.getImm();
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 395 SDValue Op2 = Op.getOperand(2);
412 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
419 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
420 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
|
| SelectionDAG.cpp | 268 /// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function
271 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2,
273 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3)
277 unsigned Op = Op1 | Op2; // Combine all of the condition bits.
292 /// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This
295 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2,
297 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3)
302 ISD::CondCode Result = ISD::CondCode(Op1 & Op2);
735 SDValue Op1, SDValue Op2,
740 SDValue Ops[] = { Op1, Op2 };
[all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonPeephole.cpp | 241 MachineOperand Op2 = MI->getOperand(S2);
242 ChangeOpInto(MI->getOperand(S1), Op2);
|
| /external/llvm/include/llvm/Analysis/ |
| ScalarEvolution.h | 582 const SCEV *getAddExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2,
587 Ops.push_back(Op2);
600 const SCEV *getMulExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2,
605 Ops.push_back(Op2);
[all...] |
| /external/llvm/lib/Analysis/ |
| ConstantFolding.cpp | [all...] |
| /external/llvm/lib/AsmParser/ |
| LLParser.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| ScheduleDAGInstrs.cpp | 776 unsigned Op2 = DefMI->findRegisterDefOperandIdx(Reg, false, true, TRI);
777 if (DefMI->getOperand(Op2).isReg())
778 DefIdx = Op2;
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineCompares.cpp | [all...] |
