/external/llvm/lib/CodeGen/SelectionDAG/ |
ResourcePriorityQueue.cpp | 59 RegPressure.resize(NumRC); 61 std::fill(RegPressure.begin(), RegPressure.end(), 0); 378 if ((RegPressure[RC->getID()] + 380 (RegPressure[RC->getID()] + 493 RegPressure[RC->getID()] += numberRCValSuccInSU(SU, RC->getID()); 504 if (RegPressure[RC->getID()] > 506 RegPressure[RC->getID()] -= numberRCValPredInSU(SU, RC->getID()); 507 else RegPressure[RC->getID()] = 0;
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ScheduleDAGRRList.cpp | 73 cl::desc("Disable regpressure priority in sched=list-ilp")); [all...] |
SelectionDAGISel.cpp | 223 if (TLI.getSchedulingPreference() == Sched::RegPressure) [all...] |
/external/llvm/include/llvm/CodeGen/ |
ResourcePriorityQueue.h | 51 /// RegPressure - Tracking current reg pressure per register class. 53 std::vector<unsigned> RegPressure;
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/external/llvm/lib/CodeGen/ |
MachineLICM.cpp | 93 SmallVector<unsigned, 8> RegPressure; 141 RegPressure.clear(); 342 RegPressure.resize(NumRC); 343 std::fill(RegPressure.begin(), RegPressure.end(), 0); 654 BackTrace.push_back(RegPressure); 797 std::fill(RegPressure.begin(), RegPressure.end(), 0); 825 RegPressure[RCId] += RCCost; 830 RegPressure[RCId] += RCCost [all...] |
/external/llvm/include/llvm/Target/ |
TargetLowering.h | 60 RegPressure, // Scheduling for lowest register pressure. [all...] |
/external/llvm/lib/Target/XCore/ |
XCoreISelLowering.cpp | 79 setSchedulingPreference(Sched::RegPressure); [all...] |
/external/llvm/lib/Target/ARM/ |
ARMISelLowering.cpp | [all...] |
/external/llvm/lib/Target/CellSPU/ |
SPUISelLowering.cpp | 477 setSchedulingPreference(Sched::RegPressure); [all...] |
/external/llvm/lib/Target/X86/ |
X86ISelLowering.cpp | 181 setSchedulingPreference(Sched::RegPressure); [all...] |