| /external/llvm/lib/Target/ARM/ |
| ARMRegisterInfo.h | 28 ARMRegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
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| ARMInstrInfo.h | 28 explicit ARMInstrInfo(const ARMSubtarget &STI);
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| ARMHazardRecognizer.h | 33 const ARMSubtarget &STI;
42 const ARMSubtarget &sti,
45 TRI(tri), STI(sti), LastMI(0) {}
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| Thumb2RegisterInfo.h | 28 Thumb2RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
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| ARMInstrInfo.cpp | 27 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
28 : ARMBaseInstrInfo(STI), RI(*this, STI) {
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| Thumb1InstrInfo.h | 27 explicit Thumb1InstrInfo(const ARMSubtarget &STI);
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| ARMFrameLowering.h | 26 const ARMSubtarget &STI;
29 explicit ARMFrameLowering(const ARMSubtarget &sti)
30 : TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), 0, 4),
31 STI(sti) {
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| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| MBlazeDisassembler.h | 33 MBlazeDisassembler(const MCSubtargetInfo &STI) :
34 MCDisassembler(STI) {
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| /external/llvm/lib/Target/PTX/ |
| PTXFrameLowering.h | 26 const PTXSubtarget &STI;
29 explicit PTXFrameLowering(const PTXSubtarget &sti)
31 STI(sti) {
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| /external/llvm/lib/Target/Sparc/ |
| SparcFrameLowering.h | 25 const SparcSubtarget &STI;
27 explicit SparcFrameLowering(const SparcSubtarget &sti)
28 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 8, 0), STI(sti) {
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| /external/llvm/include/llvm/MC/ |
| MCDisassembler.h | 58 MCDisassembler(const MCSubtargetInfo &STI) : GetOpInfo(0), SymbolLookUp(0),
60 STI(STI), CommentStream(0) {}
110 const MCSubtargetInfo &STI;
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| /external/llvm/lib/Target/MBlaze/ |
| MBlazeFrameLowering.h | 25 const MBlazeSubtarget &STI;
28 explicit MBlazeFrameLowering(const MBlazeSubtarget &sti)
29 : TargetFrameLowering(TargetFrameLowering::StackGrowsUp, 4, 0), STI(sti) {
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| /external/llvm/lib/Target/Mips/ |
| MipsFrameLowering.h | 26 const MipsSubtarget &STI;
29 explicit MipsFrameLowering(const MipsSubtarget &sti)
30 : TargetFrameLowering(StackGrowsDown, sti.hasMips64() ? 16 : 8, 0),
31 STI(sti) {
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| MipsFrameLowering.cpp | 140 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
141 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
142 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
143 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
144 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
147 unsigned RegSize = STI.isGP32bit() ? 4 : 8;
160 if (isPIC && MipsFI->globalBaseRegSet() && STI.isABI_O32() &&
188 expandLargeImm(SP, -StackSize, STI.isABI_N64(), TII, MBB, MBBI, dl);
227 if (!STI.isLittle())
271 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.h | 26 const MSP430Subtarget &STI;
29 explicit MSP430FrameLowering(const MSP430Subtarget &sti)
30 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 2, -2), STI(sti) {
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| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.h | 25 const XCoreSubtarget &STI;
27 XCoreFrameLowering(const XCoreSubtarget &STI);
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.h | 21 const HexagonSubtarget &STI;
25 explicit HexagonFrameLowering(const HexagonSubtarget &sti)
26 : TargetFrameLowering(StackGrowsDown, 8, 0), STI(sti) {
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCTargetDesc.h | 36 const MCSubtargetInfo &STI,
39 const MCSubtargetInfo &STI,
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| /external/llvm/lib/Target/MBlaze/MCTargetDesc/ |
| MBlazeMCTargetDesc.h | 33 const MCSubtargetInfo &STI,
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| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCTargetDesc.h | 34 const MCSubtargetInfo &STI,
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| /external/llvm/tools/llvm-mc/ |
| Disassembler.h | 33 MCSubtargetInfo &STI,
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| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.h | 111 X86GenericDisassembler(const MCSubtargetInfo &STI, DisassemblerMode mode,
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| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.h | 27 const X86Subtarget &STI;
29 explicit X86FrameLowering(const X86TargetMachine &tm, const X86Subtarget &sti)
31 sti.getStackAlignment(),
32 (sti.is64Bit() ? -8 : -4)),
33 TM(tm), STI(sti) {
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| /external/llvm/lib/MC/MCDisassembler/ |
| Disassembler.cpp | 72 const MCSubtargetInfo *STI = TheTarget->createMCSubtargetInfo(TripleName, CPU,
74 assert(STI && "Unable to create subtarget info!");
81 MCDisassembler *DisAsm = TheTarget->createMCDisassembler(*STI);
88 *MAI, *MII, *MRI, *STI);
94 STI, MII, Ctx, DisAsm, IP);
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| /external/llvm/lib/CodeGen/ |
| LLVMTargetMachine.cpp | 168 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
176 Context->getRegisterInfo(), STI);
182 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
183 MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), STI, *Context);
201 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), STI,
274 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
275 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(),STI,
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