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    Searched refs:ShiftOp (Results 1 - 9 of 9) sorted by null

  /external/llvm/lib/Transforms/InstCombine/
InstCombineShifts.cpp 527 BinaryOperator *ShiftOp = dyn_cast<BinaryOperator>(Op0);
528 if (ShiftOp && !ShiftOp->isShift())
529 ShiftOp = 0;
531 if (ShiftOp && isa<ConstantInt>(ShiftOp->getOperand(1))) {
532 ConstantInt *ShiftAmt1C = cast<ConstantInt>(ShiftOp->getOperand(1));
537 Value *X = ShiftOp->getOperand(0);
542 if (I.getOpcode() == ShiftOp->getOpcode()) {
559 ShiftOp->getOpcode() != Instruction::Shl)
    [all...]
  /external/v8/src/arm/
constants-arm.h 286 enum ShiftOp {
293 // Use a special code to make the distinction. The RRX ShiftOp is only used
643 inline int ShiftValue() const { return static_cast<ShiftOp>(Bits(6, 5)); }
644 inline ShiftOp ShiftField() const {
645 return static_cast<ShiftOp>(BitField(6, 5));
assembler-arm.h 414 explicit Operand(Register rm, ShiftOp shift_op, int shift_imm);
417 explicit Operand(Register rm, ShiftOp shift_op, Register rs);
437 ShiftOp shift_op() const { return shift_op_; }
442 ShiftOp shift_op_;
470 ShiftOp shift_op, int shift_imm, AddrMode am = Offset);
494 ShiftOp shift_op_;
    [all...]
disasm-arm.cc 211 ShiftOp shift = instr->ShiftField();
    [all...]
assembler-arm.cc 183 Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) {
199 Operand::Operand(Register rm, ShiftOp shift_op, Register rs) {
225 ShiftOp shift_op, int shift_imm, AddrMode am) {
    [all...]
simulator-arm.cc     [all...]
  /external/llvm/lib/Target/ARM/InstPrinter/
ARMInstPrinter.cpp 574 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
575 bool isASR = (ShiftOp & (1 << 5)) != 0;
576 unsigned Amt = ShiftOp & 0x1f;
    [all...]
  /external/llvm/lib/Target/ARM/
ARMCodeEmitter.cpp     [all...]
  /external/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGBuilder.cpp     [all...]

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