| /external/llvm/lib/Target/CellSPU/ |
| SPUInstrBuilder.h | 36 return MIB.addImm(Offset).addFrameIndex(FI);
38 return MIB.addFrameIndex(FI).addImm(Offset);
|
| SPUFrameLowering.cpp | 125 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16)
129 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
133 .addImm(FrameSize);
138 .addImm(-16)
141 .addImm(FrameSize);
150 .addImm(16);
210 .addImm(FrameSize + LinkSlotOffset)
214 .addImm(FrameSize);
219 .addImm(16)
222 .addImm(FrameSize)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrBuilder.h | 36 return MIB.addImm(Offset).addFrameIndex(FI);
38 return MIB.addFrameIndex(FI).addImm(Offset);
|
| PPCFrameLowering.cpp | 138 .addImm(UsedRegMask);
142 .addImm(UsedRegMask);
147 .addImm(UsedRegMask >> 16);
151 .addImm(UsedRegMask >> 16);
156 .addImm(UsedRegMask >> 16);
160 .addImm(UsedRegMask >> 16);
164 .addImm(UsedRegMask & 0xFFFF);
320 .addImm(FPOffset/4)
326 .addImm(LROffset / 4)
335 .addImm(FPOffset
[all...] |
| PPCRegisterInfo.cpp | 220 .addImm(CalleeAmt);
224 .addImm(CalleeAmt >> 16);
227 .addImm(CalleeAmt & 0xFFFF);
304 .addImm(FrameSize);
308 .addImm(0)
312 .addImm(0)
316 .addImm(0)
337 .addImm(maxCallFrameSize);
342 .addImm(maxCallFrameSize)
353 .addImm(maxCallFrameSize)
[all...] |
| PPCBranchSelector.cpp | 152 .addImm(PPC::InvertPredicate(Pred)).addReg(CRReg).addImm(2);
|
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 93 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
99 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
117 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
118 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
133 MIB.addImm(AM.Scale).addReg(AM.IndexReg);
137 MIB.addImm(AM.Disp);
177 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0)
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 91 HEXAGON_RESERVED_REG_1).addImm(Offset);
100 .addImm(0).addReg(HEXAGON_RESERVED_REG_2);
103 HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
108 .addImm(0)
115 addReg(FP).addImm(Offset).addReg(HEXAGON_RESERVED_REG_2);
133 HEXAGON_RESERVED_REG_1).addImm(Offset);
141 .addImm(0);
146 HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
150 .addImm(0);
156 HEXAGON_RESERVED_REG_2).addReg(FP).addImm(Offset)
[all...] |
| HexagonRegisterInfo.cpp | 194 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
201 dstReg).addReg(FrameReg).addImm(Offset);
220 TII.get(Hexagon::CONST32_Int_Real), resReg).addImm(Offset);
227 resReg).addReg(FrameReg).addImm(Offset);
240 TII.get(Hexagon::CONST32_Int_Real), resReg).addImm(Offset);
249 resReg).addReg(FrameReg).addImm(Offset);
256 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
|
| HexagonSplitTFRCondSets.cpp | 109 DestReg).addReg(SrcReg1).addImm(Immed1);
111 DestReg).addReg(SrcReg1).addImm(Immed2);
|
| HexagonFrameLowering.cpp | 149 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(0);
153 HEXAGON_RESERVED_REG_1).addImm(NumBytes);
159 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(NumBytes);
197 .addImm(NumBytes);
199 BuildMI(MBB, MBBI, dl, TII.get(Hexagon::DEALLOCFRAME)).addImm(NumBytes);
|
| /external/llvm/lib/Target/Sparc/ |
| SparcFrameLowering.cpp | 56 .addReg(SP::O6).addImm(NumBytes);
61 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
64 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
|
| SparcInstrInfo.cpp | 122 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
206 .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
248 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
250 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
307 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
310 BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
313 BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
328 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
330 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsEmitGPRestore.cpp | 71 .addImm(0);
84 .addImm(0);
|
| MipsFrameLowering.cpp | 116 .addImm(SignExtend64<16>(Inst->ImmOpnd));
119 .addImm(SignExtend64<16>(Inst->ImmOpnd));
124 .addImm(SignExtend64<16>(Inst->ImmOpnd));
185 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(-StackSize);
259 BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE)).addImm(Offset)
297 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(StackSize);
|
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 135 .addImm(Amount);
140 .addImm(Amount);
248 .addImm(Offset);
254 .addImm(Offset);
259 .addImm(Offset);
276 .addImm(Offset);
282 .addImm(Offset);
287 .addImm(Offset);
306 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
|
| XCoreInstrInfo.cpp | 344 .addImm(0);
349 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
373 .addImm(0);
386 .addImm(0);
394 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
|
| XCoreFrameLowering.cpp | 56 .addImm(Offset);
72 .addImm(Offset);
135 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
185 .addImm(0);
264 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
268 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(FrameSize);
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2RegisterInfo.cpp | 50 .addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0)
|
| Thumb1InstrInfo.cpp | 75 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
102 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
|
| ARMExpandPseudoInsts.cpp | 557 MIB.addImm(Lane);
634 LO16 = LO16.addImm(SOImmValV1);
635 HI16 = HI16.addImm(SOImmValV2);
638 LO16.addImm(Pred).addReg(PredReg).addReg(0);
639 HI16.addImm(Pred).addReg(PredReg).addReg(0);
[all...] |
| Thumb2InstrInfo.cpp | 144 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
170 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
194 .addImm(NumBytes)
195 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
201 .addImm(NumBytes >> 16)
202 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
211 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
217 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
242 .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags));
282 .addImm(ThisVal)).setMIFlags(MIFlags)
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeFrameLowering.cpp | 256 .addFrameIndex(FI).addImm(0);
264 .addFrameIndex(R17FI).addImm(0);
267 .addFrameIndex(R18FI).addImm(0);
275 .addFrameIndex(MSRFI).addImm(0);
278 .addFrameIndex(MSRFI).addImm(0);
285 .addFrameIndex(R18FI).addImm(0);
288 .addFrameIndex(R17FI).addImm(0);
294 .addFrameIndex(VFI[--i]).addImm(0);
367 .addReg(MBlaze::R1).addImm(-StackSize);
372 .addReg(MBlaze::R15).addReg(MBlaze::R1).addImm(RAOffset)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.cpp | 125 .addReg(MSP430::SPW).addImm(Amount);
134 .addReg(MSP430::SPW).addImm(Amount);
152 MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt);
210 .addReg(DstReg).addImm(-Offset);
213 .addReg(DstReg).addImm(Offset);
|
| MSP430InstrInfo.cpp | 52 .addFrameIndex(FrameIdx).addImm(0)
56 .addFrameIndex(FrameIdx).addImm(0)
80 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
83 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
278 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
|
