| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 93 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
99 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
109 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
117 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
118 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
127 MIB.addReg(AM.Base.Reg)
[all...] |
| X86FrameLowering.cpp | 175 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
190 .addReg(StackPtr)
696 .addReg(StackPtr)
736 .addReg(FramePtr, RegState::Kill)
765 .addReg(StackPtr)
790 .addReg(StackPtr)
873 .addReg(X86::EAX, RegState::Kill)
894 .addReg(StackPtr, RegState::Define | RegState::Implicit)
895 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit)
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 94 .addReg(FP).addReg(HEXAGON_RESERVED_REG_1);
96 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
99 .addReg(HEXAGON_RESERVED_REG_1)
100 .addImm(0).addReg(HEXAGON_RESERVED_REG_2);
103 HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
105 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
107 .addReg(HEXAGON_RESERVED_REG_1)
109 .addReg(HEXAGON_RESERVED_REG_2);
113 HEXAGON_RESERVED_REG_2).addReg(SrcReg)
[all...] |
| HexagonSplitTFRCondSets.cpp | 95 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
99 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
109 DestReg).addReg(SrcReg1).addImm(Immed1);
111 DestReg).addReg(SrcReg1).addImm(Immed2);
|
| HexagonRegisterInfo.cpp | 197 dstReg).addReg(FrameReg).addReg(dstReg);
201 dstReg).addReg(FrameReg).addImm(Offset);
223 resReg).addReg(FrameReg).addReg(resReg);
227 resReg).addReg(FrameReg).addImm(Offset);
243 resReg).addReg(FrameReg).addReg(resReg);
249 resReg).addReg(FrameReg).addImm(Offset);
259 dstReg).addReg(FrameReg).addReg(dstReg)
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcFrameLowering.cpp | 56 .addReg(SP::O6).addImm(NumBytes);
64 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
66 .addReg(SP::O6).addReg(SP::G1);
78 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
79 .addReg(SP::G0);
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUFrameLowering.cpp | 126 .addReg(SPU::R1);
130 .addReg(SPU::R1);
132 BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
139 .addReg(SPU::R1);
143 .addReg(SPU::R2)
144 .addReg(SPU::R1);
146 .addReg(SPU::R1)
147 .addReg(SPU::R2);
149 .addReg(SPU::R2)
152 .addReg(SPU::R2
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 137 .addReg(SrcReg)
141 .addReg(SrcReg, RegState::Kill)
146 .addReg(SrcReg)
150 .addReg(SrcReg, RegState::Kill)
155 .addReg(SrcReg)
159 .addReg(SrcReg, RegState::Kill)
163 .addReg(DstReg, RegState::Kill)
319 .addReg(PPC::X31)
321 .addReg(PPC::X1);
325 .addReg(PPC::X0
[all...] |
| PPCRegisterInfo.cpp | 219 .addReg(StackReg, RegState::Kill)
226 .addReg(TmpReg, RegState::Kill)
229 .addReg(StackReg, RegState::Kill)
230 .addReg(TmpReg);
303 .addReg(PPC::R31)
309 .addReg(PPC::X1);
313 .addReg(PPC::X1);
317 .addReg(PPC::R1);
325 .addReg(Reg, RegState::Kill)
326 .addReg(PPC::X1, RegState::Define
[all...] |
| PPCInstrInfo.cpp | 161 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
162 .addReg(Reg2, getKillRegState(Reg2IsKill))
163 .addReg(Reg1, getKillRegState(Reg1IsKill))
310 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
316 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
344 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
346 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
360 .addReg(SrcReg,
369 .addReg(PPC::R11
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2RegisterInfo.cpp | 49 .addReg(DestReg, getDefRegState(true), SubIdx)
50 .addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0)
|
| ARMExpandPseudoInsts.cpp | 391 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
393 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
395 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
397 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
428 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
465 MIB.addReg(D0);
467 MIB.addReg(D1);
469 MIB.addReg(D2);
471 MIB.addReg(D3);
521 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
[all...] |
| MLxExpansionPass.cpp | 226 .addReg(Src1Reg, getKillRegState(Src1Kill))
227 .addReg(Src2Reg, getKillRegState(Src2Kill));
230 MIB.addImm(Pred).addReg(PredReg);
233 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead));
237 MIB.addReg(TmpReg, getKillRegState(true))
238 .addReg(AccReg, getKillRegState(AccKill));
240 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
242 MIB.addImm(Pred).addReg(PredReg);
|
| Thumb2InstrInfo.cpp | 121 .addReg(SrcReg, getKillRegState(KillSrc)));
143 .addReg(SrcReg, getKillRegState(isKill))
195 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
200 .addReg(DestReg)
202 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
209 .addReg(BaseReg, RegState::Kill)
210 .addReg(DestReg, RegState::Kill)
211 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
215 .addReg(DestReg, RegState::Kill
[all...] |
| ARMFrameLowering.cpp | 292 .addReg(ARM::SP, RegState::Kill)
302 .addReg(ARM::SP, RegState::Kill));
305 .addReg(ARM::R4, RegState::Kill)
308 .addReg(ARM::R4, RegState::Kill));
323 .addReg(ARM::SP)
324 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
328 .addReg(ARM::SP));
398 .addReg(ARM::R4));
404 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0)
[all...] |
| ARMLoadStoreOptimizer.cpp | 339 .addReg(Base, getKillRegState(BaseKill)).addImm(Offset)
340 .addImm(Pred).addReg(PredReg).addReg(0);
350 .addReg(Base, getKillRegState(BaseKill))
351 .addImm(Pred).addReg(PredReg);
353 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
358 MIB.addReg(ImpDefs[i], RegState::ImplicitDefine);
780 .addReg(Base, getDefRegState(true)) // WB base register
781 .addReg(Base, getKillRegState(BaseKill))
782 .addImm(Pred).addReg(PredReg)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsExpandPseudo.cpp | 74 .addReg(Mips::V0).addReg(I->getOperand(1).getReg());
103 BuildMI(MBB, I, dl, Mtc1Tdd, *SubReg).addReg(LoReg);
104 BuildMI(MBB, I, dl, Mtc1Tdd, *(SubReg + 1)).addReg(HiReg);
116 BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(*(SubReg + N));
|
| MipsFrameLowering.cpp | 118 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg)
123 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg)
126 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(Reg).addReg(ATReg);
185 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(-StackSize);
245 BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO);
260 .addReg(Mips::GP);
286 BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO)
[all...] |
| MipsISelLowering.cpp | 828 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
829 .addReg(Mips::ZERO).addMBB(sinkMBB);
847 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
848 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
852 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
853 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 226 .addReg(FrameReg)
227 .addReg(ScratchReg, RegState::Kill);
231 .addReg(Reg, getKillRegState(isKill))
232 .addReg(FrameReg)
233 .addReg(ScratchReg, RegState::Kill);
237 .addReg(FrameReg)
238 .addReg(ScratchReg, RegState::Kill);
247 .addReg(FrameReg)
252 .addReg(Reg, getKillRegState(isKill))
253 .addReg(FrameReg
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 67 .addReg(MSP430::FPW, RegState::Kill);
71 .addReg(MSP430::SPW);
99 .addReg(MSP430::SPW).addImm(NumBytes);
157 TII.get(MSP430::MOV16rr), MSP430::SPW).addReg(MSP430::FPW);
162 .addReg(MSP430::SPW).addImm(CSSize);
171 .addReg(MSP430::SPW).addImm(NumBytes);
200 .addReg(Reg, RegState::Kill);
|
| MSP430RegisterInfo.cpp | 125 .addReg(MSP430::SPW).addImm(Amount);
134 .addReg(MSP430::SPW).addImm(Amount);
152 MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt);
210 .addReg(DstReg).addImm(-Offset);
213 .addReg(DstReg).addImm(Offset);
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 296 .addReg(MI->getOperand(2).getReg())
301 .addReg(MI->getOperand(1).getReg())
305 .addReg(IAMT)
311 .addReg(IVAL).addMBB(MBB)
312 .addReg(NDST).addMBB(loop);
317 .addReg(IAMT).addMBB(MBB)
318 .addReg(NAMT).addMBB(loop);
321 BuildMI(loop, dl, TII->get(MBlaze::ADD), NDST).addReg(DST).addReg(DST);
323 BuildMI(loop, dl, TII->get(MBlaze::SRA), NDST).addReg(DST)
[all...] |
| MBlazeFrameLowering.cpp | 273 .addReg(MBlaze::RMSR);
280 .addReg(MBlaze::R11);
367 .addReg(MBlaze::R1).addImm(-StackSize);
372 .addReg(MBlaze::R15).addReg(MBlaze::R1).addImm(RAOffset);
378 .addReg(MBlaze::R19).addReg(MBlaze::R1).addImm(FPOffset);
382 .addReg(MBlaze::R1).addReg(MBlaze::R0);
406 .addReg(MBlaze::R19).addReg(MBlaze::R0)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 621 .addReg(Reg, RegState::Debug).addImm(Offset)
638 .addReg(0U).addImm(DI->getOffset())
655 .addReg(Reg, RegState::Debug).addImm(DI->getOffset())
761 ResultReg).addReg(Op0);
[all...] |
