| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 109 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
117 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
118 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
|
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 46 .addReg(SrcReg, getKillRegState(KillSrc)));
74 .addReg(SrcReg, getKillRegState(isKill))
|
| MLxExpansionPass.cpp | 226 .addReg(Src1Reg, getKillRegState(Src1Kill))
227 .addReg(Src2Reg, getKillRegState(Src2Kill));
237 MIB.addReg(TmpReg, getKillRegState(true))
238 .addReg(AccReg, getKillRegState(AccKill));
240 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
|
| ARMLoadStoreOptimizer.cpp | 339 .addReg(Base, getKillRegState(BaseKill)).addImm(Offset)
350 .addReg(Base, getKillRegState(BaseKill))
354 | getKillRegState(Regs[i].second));
781 .addReg(Base, getKillRegState(BaseKill))
934 .addReg(Base, getKillRegState(isLd ? BaseKill : false))
937 getKillRegState(MO.isKill())));
[all...] |
| ARMExpandPseudoInsts.cpp | 547 getKillRegState(MO.isKill()));
[all...] |
| Thumb2InstrInfo.cpp | 121 .addReg(SrcReg, getKillRegState(KillSrc)));
143 .addReg(SrcReg, getKillRegState(isKill))
|
| ARMBaseInstrInfo.cpp | 655 .addReg(SrcReg, getKillRegState(KillSrc))));
676 MIB.addReg(SrcReg, getKillRegState(KillSrc));
678 MIB.addReg(SrcReg, getKillRegState(KillSrc));
764 .addReg(SrcReg, getKillRegState(isKill))
768 .addReg(SrcReg, getKillRegState(isKill))
776 .addReg(SrcReg, getKillRegState(isKill))
787 .addReg(SrcReg, getKillRegState(isKill))
791 .addReg(SrcReg, getKillRegState(isKill))
805 .addReg(SrcReg, getKillRegState(isKill))
812 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI)
[all...] |
| Thumb1FrameLowering.cpp | 323 MIB.addReg(Reg, getKillRegState(isKill));
|
| ARMFrameLowering.cpp | 620 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
624 .addReg(Regs[0].first, getKillRegState(Regs[0].second))
[all...] |
| Thumb1RegisterInfo.cpp | 271 MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 162 .addReg(Reg2, getKillRegState(Reg2IsKill))
163 .addReg(Reg1, getKillRegState(Reg1IsKill))
344 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
346 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
361 getKillRegState(isKill)),
370 getKillRegState(isKill)),
377 getKillRegState(isKill)),
386 getKillRegState(isKill)),
392 getKillRegState(isKill)),
397 getKillRegState(isKill))
[all...] |
| PPCRegisterInfo.cpp | 397 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
410 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())),
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 286 .addReg(SrcReg, getKillRegState(KillSrc));
289 .addReg(SrcReg, getKillRegState(KillSrc));
292 .addReg(SrcReg, getKillRegState(KillSrc));
308 .addReg(SrcReg, getKillRegState(isKill));
311 .addReg(SrcReg, getKillRegState(isKill));
314 .addReg(SrcReg, getKillRegState(isKill));
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 53 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
57 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
101 .addReg(SrcReg, getKillRegState(KillSrc));
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 343 .addReg(SrcReg, getKillRegState(KillSrc))
355 .addReg(SrcReg, getKillRegState(KillSrc));
371 .addReg(SrcReg, getKillRegState(isKill))
|
| XCoreRegisterInfo.cpp | 231 .addReg(Reg, getKillRegState(isKill))
252 .addReg(Reg, getKillRegState(isKill))
281 .addReg(Reg, getKillRegState(isKill))
|
| /external/llvm/lib/CodeGen/ |
| TargetInstrInfoImpl.cpp | 107 .addReg(Reg2, getKillRegState(Reg2IsKill), SubReg2)
108 .addReg(Reg1, getKillRegState(Reg1IsKill), SubReg1);
111 .addReg(Reg2, getKillRegState(Reg2IsKill), SubReg2)
112 .addReg(Reg1, getKillRegState(Reg1IsKill), SubReg1);
|
| MachineInstrBundle.cpp | 199 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeInstrInfo.cpp | 89 .addReg(SrcReg, getKillRegState(KillSrc)).addReg(MBlaze::R0);
98 BuildMI(MBB, I, DL, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill))
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUInstrInfo.cpp | 135 .addReg(SrcReg, getKillRegState(KillSrc));
170 .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
|
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 168 MIB.addReg(SrcReg, getKillRegState(KillSrc));
204 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 304 inline unsigned getKillRegState(bool B) {
|
| /external/llvm/lib/Target/PTX/ |
| PTXInstrInfo.cpp | 60 addReg(SrcReg, getKillRegState(KillSrc));
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | 376 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
380 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
384 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
[all...] |
