/external/llvm/lib/CodeGen/ |
CalcSpillWeights.cpp | 64 sub = mi->getOperand(0).getSubReg(); 66 hsub = mi->getOperand(1).getSubReg(); 68 sub = mi->getOperand(1).getSubReg(); 70 hsub = mi->getOperand(0).getSubReg();
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OptimizePHIs.cpp | 106 !SrcMI->getOperand(0).getSubReg() && 107 !SrcMI->getOperand(1).getSubReg() &&
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VirtRegMap.cpp | 143 if (MO.getSubReg()) { 165 PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg());
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TargetInstrInfoImpl.cpp | 81 unsigned SubReg0 = HasDef ? MI->getOperand(0).getSubReg() : 0; 82 unsigned SubReg1 = MI->getOperand(Idx1).getSubReg(); 83 unsigned SubReg2 = MI->getOperand(Idx2).getSubReg(); 268 if (FoldOp.getSubReg() || LiveOp.getSubReg()) 403 MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg))
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ExpandPostRAPseudos.cpp | 105 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?"); 109 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
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MachineInstr.cpp | 121 if (SubIdx && getSubReg()) 122 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); 130 if (getSubReg()) { 131 Reg = TRI.getSubReg(Reg, getSubReg()); 132 // Note that getSubReg() may return 0 if the sub-register doesn't exist. 198 getSubReg() == Other.getSubReg(); 244 OS << PrintReg(getReg(), TRI, getSubReg()); [all...] |
RegAllocFast.cpp | 662 if (!MO.getSubReg()) { 668 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0); 693 (MO.getSubReg() && MI->readsVirtualRegister(Reg))) { 734 } else if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) { [all...] |
TwoAddressInstructionPass.cpp | [all...] |
PHIElimination.cpp | 203 assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs"); 289 unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg();
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RegisterCoalescer.cpp | 221 DstSub = MI->getOperand(0).getSubReg(); 223 SrcSub = MI->getOperand(1).getSubReg(); 226 DstSub = compose(tri, MI->getOperand(0).getSubReg(), 229 SrcSub = MI->getOperand(2).getSubReg(); 259 Dst = TRI.getSubReg(Dst, DstSub); 349 Dst = TRI.getSubReg(Dst, DstSub); 354 return TRI.getSubReg(DstReg, SrcSub) == Dst; 733 UseMI->getOperand(0).getSubReg()) [all...] |
LiveDebugVariables.cpp | 185 locations[i].getSubReg() == LocMO.getSubReg()) 563 if (UI.getOperand().getSubReg() || !UI->isCopy()) 776 MO.setSubReg(locations[OldLocNo].getSubReg()); [all...] |
MachineRegisterInfo.cpp | 80 if (unsigned SubIdx = I.getOperand().getSubReg()) {
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MachineCSE.cpp | 140 if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg())
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LiveRangeEdit.cpp | 168 if (MO.getSubReg())
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LiveIntervalAnalysis.cpp | 146 assert(MI.getOperand(MOIdx).getSubReg() != MO.getSubReg() && 147 MI.getOperand(MOIdx).getSubReg() && 148 (MO.getSubReg() || MO.isImplicit())); 160 if (!MO.getSubReg() || MO.isEarlyClobber()) [all...] |
/external/llvm/include/llvm/MC/ |
MCRegisterInfo.h | 261 /// getSubReg - Returns the physical register number of sub-register "Index" 264 unsigned getSubReg(unsigned Reg, unsigned Idx) const { 273 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR)) 283 if (getSubReg(RegNo, I) == SubRegNo)
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/external/llvm/include/llvm/CodeGen/ |
MachineInstr.h | 623 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg(); 635 getOperand(0).getSubReg() == getOperand(1).getSubReg(); [all...] |
MachineOperand.h | 242 unsigned getSubReg() const { 301 return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
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/external/llvm/lib/Target/ARM/ |
ARMExpandPseudoInsts.cpp | 354 D0 = TRI->getSubReg(Reg, ARM::dsub_0); 355 D1 = TRI->getSubReg(Reg, ARM::dsub_1); 356 D2 = TRI->getSubReg(Reg, ARM::dsub_2); 357 D3 = TRI->getSubReg(Reg, ARM::dsub_3); 359 D0 = TRI->getSubReg(Reg, ARM::dsub_0); 360 D1 = TRI->getSubReg(Reg, ARM::dsub_2); 361 D2 = TRI->getSubReg(Reg, ARM::dsub_4); 362 D3 = TRI->getSubReg(Reg, ARM::dsub_6); 365 D0 = TRI->getSubReg(Reg, ARM::dsub_1); 366 D1 = TRI->getSubReg(Reg, ARM::dsub_3) [all...] |
ARMMCInstLower.cpp | 74 assert(!MO.getSubReg() && "Subregs should be eliminated!");
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Thumb2ITBlockPass.cpp | 117 assert(MI->getOperand(0).getSubReg() == 0 && 118 MI->getOperand(1).getSubReg() == 0 &&
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/external/llvm/lib/Target/ARM/InstPrinter/ |
ARMInstPrinter.cpp | [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonPeephole.cpp | 169 if (Src.getSubReg() != Hexagon::subreg_loreg)
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HexagonInstrInfo.cpp | 333 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) { 335 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg, 339 BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg, 341 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg, [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCMCInstLower.cpp | 145 assert(!MO.getSubReg() && "Subregs should be eliminated!");
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