| /external/openssl/crypto/sha/asm/ |
| sha1-mips.s | 41 lwr $8,0($5)
55 lwr $9,1*4+0($5)
79 lwr $10,2*4+0($5)
103 lwr $11,3*4+0($5)
127 lwr $12,4*4+0($5)
151 lwr $13,5*4+0($5)
175 lwr $14,6*4+0($5)
199 lwr $15,7*4+0($5)
223 lwr $16,8*4+0($5)
247 lwr $17,9*4+0($5
[all...] |
| sha256-mips.s | 51 lwr $8,0($5)
53 lwr $9,4($5)
105 lwr $10,8($5)
157 lwr $11,12($5)
209 lwr $12,16($5)
261 lwr $13,20($5)
313 lwr $14,24($5)
365 lwr $15,28($5)
417 lwr $16,32($5)
469 lwr $17,36($5
[all...] |
| sha1-mips.pl | 13 # to deploy lwl/lwr pair to load unaligned input. One could have
112 lwr @X[$j],$j*4+$LSB($inp)
289 lwr @X[0],$LSB($inp)
|
| /external/openssl/crypto/aes/asm/ |
| aes-mips.s | 45 lwr $12,3($1) # Te1[s1>>16]
46 lwr $13,3($2) # Te1[s2>>16]
47 lwr $14,3($24) # Te1[s3>>16]
48 lwr $15,3($25) # Te1[s0>>16]
66 lwr $16,2($1) # Te2[s2>>8]
67 lwr $17,2($2) # Te2[s3>>8]
68 lwr $18,2($24) # Te2[s0>>8]
69 lwr $19,2($25) # Te2[s1>>8]
87 lwr $20,1($1) # Te3[s3]
88 lwr $21,1($2) # Te3[s0
[all...] |
| aes-mips.pl | 18 # additional rotations. Rotations are implemented with lwl/lwr pairs,
146 lwr $t0,2($i0) # Te1[s1>>16]
147 lwr $t1,2($i1) # Te1[s2>>16]
148 lwr $t2,2($i2) # Te1[s3>>16]
149 lwr $t3,2($i3) # Te1[s0>>16]
167 lwr $t4,1($i0) # Te2[s2>>8]
168 lwr $t5,1($i1) # Te2[s3>>8]
169 lwr $t6,1($i2) # Te2[s0>>8]
170 lwr $t7,1($i3) # Te2[s1>>8]
188 lwr $t8,0($i0) # Te3[s3
[all...] |
| /external/llvm/test/MC/MBlaze/ |
| mblaze_memory.s | 44 # CHECK: lwr
47 lwr r1, r2, r3
|
| /development/ndk/platforms/android-9/arch-mips/include/machine/ |
| asm.h | 69 #define LWHI lwr
78 #define LWLO lwr
|
| /prebuilts/gcc/darwin-x86/mips/mipsel-linux-android-4.4.3/sysroot/usr/include/machine/ |
| asm.h | 69 #define LWHI lwr
78 #define LWLO lwr
|
| /prebuilts/gcc/linux-x86/mips/mipsel-linux-android-4.4.3/sysroot/usr/include/machine/ |
| asm.h | 69 #define LWHI lwr
78 #define LWLO lwr
|
| /external/qemu/target-mips/ |
| helper.h | 14 DEF_HELPER_3(lwr, tl, tl, tl, int)
|
| translate.c | [all...] |
| /external/v8/src/mips/ |
| disasm-mips.cc | 889 case LWR:
890 Format(instr, "lwr 'rt, 'imm16s('rs)");
|
| assembler-mips.h | 750 void lwr(Register rd, const MemOperand& rs);
[all...] |
| assembler-mips.cc | 1404 void Assembler::lwr(Register rd, const MemOperand& rs) { function in class:v8::Assembler
[all...] |
| code-stubs-mips.cc | [all...] |
| /external/webkit/Source/JavaScriptCore/assembler/ |
| MacroAssemblerMIPS.h | 539 lwr dest, address.offset+3(addrTemp)
542 lwr dest, address.offset(addrTemp)
548 m_assembler.lwr(dest, addrTempRegister, address.offset + 3);
551 m_assembler.lwr(dest, addrTempRegister, address.offset);
576 m_assembler.lwr(dest, addrTempRegister, 3);
579 m_assembler.lwr(dest, addrTempRegister, 0);
[all...] |
| MIPSAssembler.h | 434 void lwr(RegisterID rt, RegisterID rs, int offset) function in class:JSC::MIPSAssembler
|
| /external/v8/test/cctest/ |
| test-assembler-mips.cc | 837 // Test LWL, LWR, SWL and SWR instructions.
882 // Test all combinations of LWR and vAddr.
884 __ lwr(t0, MemOperand(a0, OFFSET_OF(T, mem_init)) );
888 __ lwr(t1, MemOperand(a0, OFFSET_OF(T, mem_init) + 1) );
892 __ lwr(t2, MemOperand(a0, OFFSET_OF(T, mem_init) + 2) );
896 __ lwr(t3, MemOperand(a0, OFFSET_OF(T, mem_init) + 3) );
[all...] |
| /external/sqlite/dist/orig/ |
| sqlite3.c | 53882 int lwr, upr, idx; local
[all...] |
| /external/sqlite/dist/ |
| sqlite3.c | 53893 int lwr, upr, idx; local
[all...] |
