| /external/oprofile/events/mips/24K/ |
| events | 36 event:0x12 counters:0 um:zero minimum:500 name:ALL_STALLS : 18-0 Stall cycles, including ALU and IFU
43 event:0x19 counters:0 um:zero minimum:500 name:IFU_STALLS : 25-0 IFU stall cycles
53 # Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events.
55 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
56 event:0x26 counters:0 um:zero minimum:500 name:SYNC_STALLS : 38-0 SYNC stall cycles
58 event:0x28 counters:0 um:zero minimum:500 name:UNCACHED_STALLS : 40-0 Uncached stall cycles
59 event:0x29 counters:0 um:zero minimum:500 name:MDU_STALLS : 41-0 MDU stall cycles
60 event:0x2a counters:0 um:zero minimum:500 name:CP2_STALLS : 42-0 CP2 stall cycles
61 event:0x2b counters:0 um:zero minimum:500 name:ISPRAM_STALLS : 43-0 ISPRAM stall cycles
62 event:0x2c counters:0 um:zero minimum:500 name:CACHE_INSN_STALLS : 44-0 Stall cycless due to CACHE instruction
[all...] |
| /external/oprofile/events/mips/34K/ |
| events | 36 event:0x12 counters:0 um:zero minimum:500 name:ALL_STALLS : 18-0 Stall cycles, including ALU and IFU
43 event:0x19 counters:0 um:zero minimum:500 name:IFU_STALLS : 25-0 IFU stall cycles
57 # Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events.
59 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
62 event:0x28 counters:0 um:zero minimum:500 name:UNCACHED_STALLS : 40-0 Uncached stall cycles
63 event:0x29 counters:0 um:zero minimum:500 name:MDU_STALLS : 41-0 MDU stall cycles
64 event:0x2a counters:0 um:zero minimum:500 name:CP2_STALLS : 42-0 CP2 stall cycles
65 event:0x2b counters:0 um:zero minimum:500 name:ISPRAM_STALLS : 43-0 ISPRAM stall cycles
66 event:0x2c counters:0 um:zero minimum:500 name:CACHE_INSN_STALLS : 44-0 Stall cycless due to CACHE instructions
67 event:0x2d counters:0 um:zero minimum:500 name:LOAD_USE_STALLS : 45-0 Load to use stall cycle
[all...] |
| /external/oprofile/events/mips/1004K/ |
| events | 36 event:0x12 counters:0 um:zero minimum:500 name:ALL_STALLS : 18-0 Stall cycles, including ALU and IFU
43 event:0x19 counters:0 um:zero minimum:500 name:IFU_STALLS : 25-0 IFU stall cycles
55 event:0x24 counters:0 um:zero minimum:500 name:INTERVENTION_STALLS : 36-0 Cache coherence intervention processing stall cycles
58 # Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events.
60 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
63 event:0x28 counters:0 um:zero minimum:500 name:UNCACHED_STALLS : 40-0 Uncached stall cycles
64 event:0x29 counters:0 um:zero minimum:500 name:MDU_STALLS : 41-0 MDU stall cycles
65 event:0x2a counters:0 um:zero minimum:500 name:CP2_STALLS : 42-0 CP2 stall cycles
66 event:0x2b counters:0 um:zero minimum:500 name:ISPRAM_STALLS : 43-0 ISPRAM stall cycles
67 event:0x2c counters:0 um:zero minimum:500 name:CACHE_INSN_STALLS : 44-0 Stall cycless due to CACHE instruction
[all...] |
| /external/oprofile/events/mips/rm7000/ |
| events | 13 event:0x09 counters:0,1 um:zero minimum:500 name:STALL_CYCLES : Stall cycles
25 event:0x15 counters:0,1 um:zero minimum:500 name:DCACHE_MISS_STALL_CYCLES : Dcache miss stall cycles (cycles where both cache miss tokens taken and a third try is requested)
31 event:0x1c counters:0,1 um:zero minimum:500 name:WRITE_BUFFER_FULL_STALL_CYCLES : Write buffer full stall cycles
32 event:0x1d counters:0,1 um:zero minimum:500 name:CACHE_INSTRUCTION_STALL_CYCLES : Cache instruction stall cycles
33 event:0x1e counters:0,1 um:zero minimum:500 name:MULTIPLIER_STALL_CYCLES : Multiplier stall cycles
34 event:0x1f counters:0,1 um:zero minimum:500 name:STALL_CYCLES_PENDING_NON_BLKING_LOAD : Stall cycles due to pending non-blocking loads - stall start of exception
|
| /external/tremolo/Tremolo/ |
| bitwiseARM.s | 89 @ Stall
90 @ Stall
93 @ Stall
94 @ Stall
107 @ Stall
135 @ stall
136 @ stall
139 @ stall
140 @ stall
147 @ stall
[all...] |
| dpen.s | 102 @ stall Xscale
127 @ stall Xscale
144 @ stall Xscale
159 @ stall Xscale
185 @ stall Xscale
204 @ stall Xscale
217 @ stall Xscale
474 @ stall
475 @ stall Xscale
479 @ stall Xscal
[all...] |
| mdctARM.s | 96 @ stall
97 @ stall (Xscale)
164 @ stall
165 @ stall (Xscale)
323 @ stall
324 @ stall ?
327 @ stall ?
330 @ stall ?
347 @ stall
348 @ stall
[all...] |
| mdctLARM.s | 96 @ stall
97 @ stall (Xscale)
164 @ stall
165 @ stall (Xscale)
485 @ stall Xscale
551 @ stall Xscale
574 @ stall Xscale
628 @ stall Xscale
703 @ stall Xscale
997 @ stall XScal
[all...] |
| /external/oprofile/events/x86-64/family11h/ |
| events | 71 event:0x87 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_FETCH_STALL : Instruction fetch stall
99 event:0xd2 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_BRANCH_ABORT : Dispatch stall from branch abort to retire
100 event:0xd3 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_SERIALIZATION : Dispatch stall for serialization
101 event:0xd4 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_SEGMENT_LOAD : Dispatch stall for segment load
102 event:0xd5 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_REORDER_BUFFER_FULL : Dispatch stall for reorder buffer full
103 event:0xd6 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_RESERVATION_STATION_FULL : Dispatch stall when reservation stations are full
104 event:0xd7 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_FPU_FULL : Dispatch stall when FPU is full
105 event:0xd8 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_LS_FULL : Dispatch stall when LS is full
106 event:0xd9 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_WAITING_FOR_ALL_QUIET : Dispatch stall when waiting for all to be quiet
107 event:0xda counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RESYNC : Dispatch stall for far transfer or resync to retir
[all...] |
| /external/oprofile/events/x86-64/hammer/ |
| events | 71 event:0x87 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_FETCH_STALL : Instruction fetch stall
94 event:0xd2 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_BRANCH_ABORT : Dispatch stall from branch abort to retire
95 event:0xd3 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_SERIALIZATION : Dispatch stall for serialization
96 event:0xd4 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_SEGMENT_LOAD : Dispatch stall for segment load
97 event:0xd5 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_REORDER_BUFFER_FULL : Dispatch stall for reorder buffer full
98 event:0xd6 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_RESERVATION_STATION_FULL : Dispatch stall when reservation stations are full
99 event:0xd7 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_FPU_FULL : Dispatch stall when FPU is full
100 event:0xd8 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_LS_FULL : Dispatch stall when LS is full
101 event:0xd9 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_WAITING_FOR_ALL_QUIET : Dispatch stall when waiting for all to be quiet
102 event:0xda counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RESYNC : Dispatch stall for far transfer or resync to retir
[all...] |
| /external/openssl/crypto/sha/asm/ |
| sha1-armv4-large.s | 180 eor r11,r11,r12 @ 1 cycle stall
197 eor r11,r11,r12 @ 1 cycle stall
214 eor r11,r11,r12 @ 1 cycle stall
231 eor r11,r11,r12 @ 1 cycle stall
253 eor r11,r11,r12 @ 1 cycle stall
269 eor r11,r11,r12 @ 1 cycle stall
285 eor r11,r11,r12 @ 1 cycle stall
301 eor r11,r11,r12 @ 1 cycle stall
317 eor r11,r11,r12 @ 1 cycle stall
340 eor r11,r11,r12 @ 1 cycle stall
[all...] |
| sha1-armv4-large.pl | 83 eor $t2,$t2,$t3 @ 1 cycle stall
|
| /external/oprofile/events/mips/rm9000/ |
| events | 12 event:0x09 counters:0,1 um:zero minimum:500 name:STALL_CYCLES : Stall cycles
24 event:0x15 counters:0,1 um:zero minimum:500 name:DCACHE_MISS_STALL_CYCLES : Dcache-miss stall cycles
30 event:0x1b counters:0,1 um:zero minimum:500 name:WRITE_BUFFER_FULL_STALL_CYCLES : Stall cycles due to a full write buffer
31 event:0x1c counters:0,1 um:zero minimum:500 name:CACHE_INSN_STALL_CYCLES : Stall cycles due to cache instructions
32 event:0x1e counters:0,1 um:zero minimum:500 name:NONBLOCKING_LOAD_PENDING_EXCEPTION_STALL_CYCLES : Stall cycles due to pending non-blocking loads - stall start of exception
|
| /external/oprofile/events/mips/74K/ |
| events | 21 event:0x3 counters:0,2 um:zero minimum:500 name:REDIRECT_STALLS : 3-0 Stall cycles due to register indirect jumps (including non-predicted JR $31), ERET/WAIT instructions, and IFU determined exception
25 event:0x7 counters:0,2 um:zero minimum:500 name:ICACHE_MISS_STALLS : 7-0 Instruction cache miss stall cycles
26 event:0x8 counters:0,2 um:zero minimum:500 name:UNCACHED_IFETCH_STALLS : 8-0 Uncached instruction fetch stall cycles
31 event:0xd counters:0,2 um:zero minimum:500 name:DDQ0_FULL_DR_STALLS : 13-0 DR stage stall cycles due to DDQ0 (ALU out-of-order dispatch queue) full
32 event:0xe counters:0,2 um:zero minimum:500 name:ALCB_FULL_DR_STALLS : 14-0 DR stage stall cycles due to ALCB (ALU completion buffers) full
33 event:0xf counters:0,2 um:zero minimum:500 name:CLDQ_FULL_DR_STALLS : 15-0 DR stage stall cycles due to CLDQ (data comming back from FPU) full
48 event:0x1e counters:0,2 um:zero minimum:500 name:FSB_FULL_STALLS : 30-0 Pipe stall cycles due to FSB full
49 event:0x1f counters:0,2 um:zero minimum:500 name:LDQ_FULL_STALLS : 31-0 Pipe stall cycles due to LDQ full
50 event:0x20 counters:0,2 um:zero minimum:500 name:WBB_FULL_STALLS : 32-0 Pipe stall cycles due to WBB full
107 event:0x40d counters:1,3 um:zero minimum:500 name:DDQ1_FULL_DR_STALLS : 13-1 DR stage stall cycles due to DDQ1 (AGEN out-of-order dispatch queue) ful
[all...] |
| /external/oprofile/events/mips/5K/ |
| events | 35 event:0xa counters:1 um:zero minimum:500 name:CONFLICT_STALL_M_STAGE : Instruction stall in M stage due to scheduling conflicts
|
| /external/oprofile/events/i386/westmere/ |
| events | 11 event:0x04 counters:0,1,2,3 um:x07 minimum:200000 name:SB_DRAIN : All Store buffer stall cycles
44 event:0x80 counters:0,1,2,3 um:l1i minimum:2000000 name:L1I : L1I instruction fetch stall cycles
47 event:0x87 counters:0,1,2,3 um:ild_stall minimum:2000000 name:ILD_STALL : Any Instruction Length Decoder stall cycles
50 event:0xa2 counters:0,1,2,3 um:resource_stalls minimum:2000000 name:RESOURCE_STALLS : Resource related stall cycles
74 event:0xd2 counters:0,1,2,3 um:rat_stalls minimum:2000000 name:RAT_STALLS : All RAT stall cycles
75 event:0xd4 counters:0,1,2,3 um:x01 minimum:2000000 name:SEG_RENAME_STALLS : Segment rename stall cycles
86 event:0xf6 counters:0,1,2,3 um:x01 minimum:2000000 name:SQ_FULL_STALL_CYCLES : Super Queue full stall cycles
|
| unit_masks | 95 0x01 lcp Length Change Prefix stall cycles
96 0x02 mru Stall cycles due to BPU MRU bypass
97 0x04 iq_full Instruction Queue full stall cycles
98 0x08 regen Regen stall cycles
99 0x0f any Any Instruction Length Decoder stall cycles
128 0x04 cycles_stalled L1I instruction fetch stall cycles
231 0x01 flags Flag stall cycles
232 0x02 registers Partial register stall cycles
234 0x08 scoreboard Scoreboard stall cycles
235 0x0f any All RAT stall cycle
[all...] |
| /bootable/bootloader/legacy/arch_msm7k/ |
| hsusb.c | 290 /* per spec, STALL is valid if there is not alt func */
291 goto stall;
311 dprintf("STALL %s %b %b %d %d %d\n",
315 stall:
|
| /external/sonivox/arm-hybrid-22k/lib_src/ |
| ARM-E_interpolate_loop_gnu.s | 92 ADD tmp2, phaseIncrement, phaseFrac @ increment pointer here to avoid pipeline stall
|
| ARM-E_interpolate_noloop_gnu.s | 84 ADD tmp2, phaseIncrement, phaseFrac @ increment pointer here to avoid pipeline stall
|
| /external/sonivox/arm-wt-22k/lib_src/ |
| ARM-E_interpolate_loop_gnu.s | 92 ADD tmp2, phaseIncrement, phaseFrac @ increment pointer here to avoid pipeline stall
|
| ARM-E_interpolate_noloop_gnu.s | 84 ADD tmp2, phaseIncrement, phaseFrac @ increment pointer here to avoid pipeline stall
|
| /external/oprofile/events/i386/nehalem/ |
| unit_masks | 206 0x02 mru Instruction Length Decoder stall cycles due to Brand Prediction Unit (PBU) Most Recently Used (MRU) bypass
207 0x04 iq_full Stall cycles due to a full instruction queue
234 0x02 load Counts the cycles of stall due to lack of load buffer for load operation
236 0x08 store This event counts the number of cycles that a resource related stall will occur due to the number of store instructions reaching the limit of the pipeline, (i
237 0x10 rob_full Counts the cycles of stall due to reorder buffer full
315 0x01 flags Counts the number of cycles during which execution stalled due to several reasons, one of which is a partial flag register stall
318 0x08 scoreboard Counts the cycles where we stall due to microarchitecturally required serialization
319 0x0F any Counts all Register Allocation Table stall cycles due to: Cycles when ROB read port stalls occurred, which did not allow new micro-ops to enter the execution pipe
|
| /external/openssl/crypto/bn/asm/ |
| armv4-gf2m.s | 61 eor r5,r5,r7,lsl#3 @ stall
|
| /external/blktrace/btreplay/ |
| btreplay.c | 1170 * stall - Stall for the number of nanoseconds requested
1174 static void stall(struct thr_info *tip, long long oclock) function
1182 fprintf(tip->vfp, " stall(%lld.%09lld, %lld.%09lld)\n",
1192 fprintf(tip->vfp, "++ stall(%lld.%09lld) ++\n",
1265 stall(tip, bunch->hdr.time_stamp - genesis);
[all...] |
