| /external/llvm/test/CodeGen/XCore/ |
| misc-intrinsics.ll | 8 declare i32 @llvm.xcore.sext(i32, i32)
47 define i32 @sext(i32 %a, i32 %b) {
48 ; CHECK: sext:
49 ; CHECK: sext r0, r1
50 %result = call i32 @llvm.xcore.sext(i32 %a, i32 %b)
56 ; CHECK: sext r0, 4
57 %result = call i32 @llvm.xcore.sext(i32 %a, i32 4)
|
| /external/llvm/test/Transforms/IndVarSimplify/ |
| 2011-09-27-hoistsext.ll | 2 ; Test indvars' ability to hoist new sext created by WidenIV.
8 ; CHECK: sext
9 ; CHECK: sext
14 ; CHECK-NOT: sext
19 %idxprom177 = sext i32 %add174 to i64
|
| elim-extend.ll | 6 ; IV rewrite only removes one sext. WidenIVs removes all three.
11 ; CHECK-NOT: sext
16 %preofs = sext i32 %iv to i64
20 %postofs = sext i32 %postiv to i64
24 %postofsnsw = sext i32 %postivnsw to i64
43 ; CHECK-NOT: sext
48 %preofs = sext i32 %iv to i64
52 %postofs = sext i32 %postiv to i64
56 %postofsnsw = sext i32 %postivnsw to i64
80 ; CHECK-NOT: sext
[all...] |
| 2009-04-14-shorten_iv_vars.ll | 1 ; RUN: opt < %s -indvars -S | not grep {sext}
20 %2 = sext i32 %i.0.reg2mem.0 to i64 ; <i64> [#uses=1]
24 %6 = sext i32 %i.0.reg2mem.0 to i64 ; <i64> [#uses=1]
28 %10 = sext i32 %i.0.reg2mem.0 to i64 ; <i64> [#uses=1]
35 %16 = sext i32 %15 to i64 ; <i64> [#uses=1]
40 %21 = sext i32 %20 to i64 ; <i64> [#uses=1]
44 %25 = sext i32 %13 to i64 ; <i64> [#uses=1]
51 %31 = sext i32 %30 to i64 ; <i64> [#uses=1]
56 %36 = sext i32 %35 to i64 ; <i64> [#uses=1]
60 %40 = sext i32 %28 to i64 ; <i64> [#uses=1
[all...] |
| /external/llvm/test/Transforms/InstCombine/ |
| vector-casts.ll | 29 %sext = sext <4 x i1> %cmp to <4 x i32>
31 %sext5 = sext <4 x i1> %cmp4 to <4 x i32>
32 %and = and <4 x i32> %sext, %sext5
43 %sext = sext <4 x i1> %cmp to <4 x i32>
45 %sext5 = sext <4 x i1> %cmp4 to <4 x i32>
46 %or = or <4 x i32> %sext, %sext5
58 %sext = sext <4 x i1> %cmp to <4 x i32>
[all...] |
| 2008-01-21-MismatchedCastAndCompare.ll | 14 %a = sext i8 %A to i32
15 %b = sext i8 %B to i32
|
| apint-zext2.ll | 7 %c2 = sext i533 %c1 to i1024
|
| zext.ll | 6 %c2 = sext i32 %c1 to i64 ; <i64> [#uses=1]
|
| /external/llvm/test/CodeGen/PowerPC/ |
| mulhs.ll | 10 %tmp.1 = sext i32 %a to i64 ; <i64> [#uses=1]
11 %tmp.3 = sext i32 %b to i64 ; <i64> [#uses=1]
|
| /external/llvm/test/CodeGen/Thumb2/ |
| thumb2-sxt-uxt.ll | 6 %r = sext i16 %z to i32
13 %r = sext i8 %z to i32
|
| /external/llvm/test/CodeGen/X86/ |
| avx2-cmp.ll | 6 %x = sext <8 x i1> %bincmp to <8 x i32>
13 %x = sext <4 x i1> %bincmp to <4 x i64>
20 %x = sext <16 x i1> %bincmp to <16 x i16>
27 %x = sext <32 x i1> %bincmp to <32 x i8>
34 %x = sext <8 x i1> %bincmp to <8 x i32>
41 %x = sext <4 x i1> %bincmp to <4 x i64>
48 %x = sext <16 x i1> %bincmp to <16 x i16>
55 %x = sext <32 x i1> %bincmp to <32 x i8>
|
| 2006-10-09-CycleInDAG.ll | 5 %tmp201.upgrd.1 = sext i32 %tmp201 to i64 ; <i64> [#uses=1]
|
| vec_compare.ll | 10 %D = sext <4 x i1> %C to <4 x i32>
21 %D = sext <4 x i1> %C to <4 x i32>
31 %D = sext <4 x i1> %C to <4 x i32>
41 %D = sext <4 x i1> %C to <4 x i32>
|
| widen_conv-2.ll | 9 %signext = sext <2 x i16> %src to <2 x i32> ; <<12 x i8>> [#uses=1]
|
| x86-64-arg.ll | 12 %tmp12 = sext i16 %X to i32 ; <i32> [#uses=1]
|
| sse-commute.ll | 14 %sext = sext <4 x i1> %cmp to <4 x i32> ; <<4 x i32>> [#uses=1]
15 %and = and <4 x i32> %tmp6, %sext ; <<4 x i32>> [#uses=1]
|
| /external/llvm/test/CodeGen/Generic/ |
| 2006-04-28-Sign-extend-bool.ll | 7 %tmp99100 = sext i8 %tmp99.upgrd.1 to i32 ; <i32> [#uses=1]
|
| i128-arith.ll | 5 %tmp1 = sext i64 %y to i128
|
| /external/llvm/test/Transforms/ConstProp/ |
| 2006-12-01-bool-casts.ll | 7 %A = sext i1 true to i32 ; <i32> [#uses=1]
|
| /external/llvm/test/Analysis/ScalarEvolution/ |
| 2009-04-22-TruncCast.ll | 4 %A = sext i8 %x to i32
10 %A = sext i16 %x to i32
16 %A = sext i16 %x to i32
|
| sext-iv-0.ll | 3 ; Convert (sext {-128,+,1}) to {sext(-128),+,sext(1)}, since the
23 %2 = sext i9 %1 to i64 ; <i64> [#uses=1]
29 %6 = sext i8 %0 to i64 ; <i64> [#uses=1]
|
| /external/llvm/test/CodeGen/ARM/ |
| ldr_ext.ll | 20 %tmp1.s = sext i8 %tmp.s to i32
27 %tmp1.s = sext i16 %tmp.s to i32
35 %tmp1.s = sext i16 %tmp.s to i32
|
| vfcmp.ll | 13 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
24 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
35 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
47 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
59 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
71 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
83 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
97 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
110 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
124 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32
[all...] |
| vicmp.ll | 16 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
27 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
38 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
49 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
60 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
71 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
81 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
91 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
101 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
111 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32
[all...] |
| /external/llvm/test/CodeGen/CellSPU/ |
| sext128.ll | 9 %0 = sext i64 %a to i128
23 %0 = sext i32 %a to i128
38 %1 = sext i32 %0 to i128
59 %0 = sext i8 %u to i128
69 %0 = sext i16 %u to i128
|
