| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
|
| DAGCombiner.cpp | [all...] |
| TargetLowering.cpp | [all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 83 case MVT::v2i64: return "MVT::v2i64";
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 403 addRegisterClass(MVT::v2i64, SPU::VECREGRegisterClass);
450 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMISelLowering.cpp | 471 addQRTypeForNEON(MVT::v2i64);
522 // Neon does not support some operations on v1i64 and v2i64 types.
527 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
534 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
[all...] |
| /external/llvm/include/llvm/ |
| Intrinsics.td | 131 def llvm_v2i64_ty : LLVMType<v2i64>; // 2 x i64
|
| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.td | 460 def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
|
| README.txt | [all...] |
| X86FastISel.cpp | 268 case MVT::v2i64:
[all...] |
| X86InstrCompiler.td | [all...] |
| /external/clang/utils/ABITest/ |
| ABITestGen.py | 462 action="store", type=str, default='v2i16, v1i64, v2i32, v4i16, v8i8, v2f32, v2i64, v4i32, v8i16, v16i8, v2f64, v4f32, v16f32', metavar="N")
|
| /external/llvm/test/CodeGen/CellSPU/ |
| select_bits.ll | 11 ; v2i64
|
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 294 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
[all...] |
| /external/clang/lib/CodeGen/ |
| CGBuiltin.cpp | [all...] |
