| /external/qemu/ |
| translate-all.c | 89 tcg_set_frame(&tcg_ctx, TCG_AREG0, offsetof(CPUState, temp_buf),
99 int cpu_gen_code(CPUState *env, TranslationBlock *tb, int *gen_code_size_ptr)
174 CPUState *env, unsigned long searched_pc)
|
| kqemu.c | 126 static void kqemu_update_cpuid(CPUState *env)
163 int kqemu_init(CPUState *env)
253 void kqemu_flush_page(CPUState *env, target_ulong addr)
262 void kqemu_flush(CPUState *env, int global)
268 void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr)
293 void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr)
404 static void restore_native_fp_frstor(CPUState *env)
429 static void save_native_fp_fsave(CPUState *env)
454 static void restore_native_fp_fxrstor(CPUState *env)
480 static void save_native_fp_fxsave(CPUState *env
[all...] |
| exec.c | 124 CPUState *first_cpu;
127 CPUState *cpu_single_env;
393 static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
538 CPUState *env = opaque;
548 CPUState *env = opaque;
565 CPUState *qemu_get_cpu(int cpu)
567 CPUState *env = first_cpu;
578 void cpu_exec_init(CPUState *env)
580 CPUState **penv;
638 void tb_flush(CPUState *env1
[all...] |
| poison.h | 37 #pragma GCC poison CPUState
|
| arm-semi.c | 110 static inline uint32_t set_swi_errno(CPUState *env, uint32_t code)
124 static void arm_semi_cb(CPUState *env, target_ulong ret, target_ulong err)
154 static void arm_semi_flen_cb(CPUState *env, target_ulong ret, target_ulong err)
176 uint32_t do_arm_semihosting(CPUState *env)
186 CPUState *ts = env;
|
| monitor.c | 85 CPUState *mon_cpu;
112 CPUState *cenv;
359 CPUState *env;
370 static CPUState *mon_get_cpu(void)
381 CPUState *env;
396 CPUState *env;
455 CPUState *env;
639 CPUState *env;
840 CPUState *env;
1245 CPUState *env
[all...] |
| cpu-defs.h | 193 CPUState *next_cpu; /* next CPU sharing TB cache */ \
|
| disas.c | 341 static CPUState *monitor_disas_env;
365 void monitor_disas(Monitor *mon, CPUState *env,
|
| /external/qemu/target-i386/ |
| hax-darwin.c | 268 int hax_sync_fpu(CPUState *env, struct fx_layout *fl, int set)
283 int hax_sync_msr(CPUState *env, struct hax_msr_data *msrs, int set)
297 int hax_sync_vcpu_state(CPUState *env, struct vcpu_state_t *state, int set)
312 int hax_inject_interrupt(CPUState *env, int vector)
|
| cpu.h | 45 #define CPUState struct CPUX86State
872 static inline int cpu_mmu_index (CPUState *env)
886 static inline int is_cpu_user(CPUState *env)
892 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
905 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
910 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
919 void apic_init_reset(CPUState *env);
920 void apic_sipi(CPUState *env);
921 void do_cpu_init(CPUState *env);
922 void do_cpu_sipi(CPUState *env)
[all...] |
| hax-windows.c | 399 int hax_sync_fpu(CPUState *env, struct fx_layout *fl, int set)
432 int hax_sync_msr(CPUState *env, struct hax_msr_data *msrs, int set)
464 int hax_sync_vcpu_state(CPUState *env, struct vcpu_state_t *state, int set)
497 int hax_inject_interrupt(CPUState *env, int vector)
|
| exec.h | 341 static inline int cpu_has_work(CPUState *env)
354 static inline int cpu_halted(CPUState *env) {
368 static inline void cpu_load_efer(CPUState *env, uint64_t val)
|
| translate.c | 279 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_B_OFFSET);
281 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
285 tcg_gen_st16_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
289 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
292 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
296 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, regs[reg]));
301 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
321 tcg_gen_st16_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
325 tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
328 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET)
[all...] |
| helper.c | 601 cpu_x86_dump_seg_cache(CPUState *env, FILE *f,
655 void cpu_dump_state(CPUState *env, FILE *f,
[all...] |
| /external/qemu/target-mips/ |
| helper.c | 38 int no_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
47 int fixed_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
65 int r4k_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
102 static int get_physical_address (CPUState *env, target_phys_addr_t *physical,
204 static void raise_mmu_exception(CPUState *env, target_ulong address,
256 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
270 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
314 target_phys_addr_t cpu_mips_translate_address(CPUState *env, target_ulong address, int rw)
372 void do_interrupt (CPUState *env)
595 void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra
[all...] |
| /external/qemu/target-arm/ |
| helper.c | 323 static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)
350 static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg)
576 void do_interrupt (CPUState *env)
581 int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
595 void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
600 uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
607 void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
612 uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
618 void switch_mode(CPUState *env, int mode)
624 void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val
[all...] |
| cpu.h | 26 #define CPUState struct CPUARMState
464 static inline int cpu_mmu_index (CPUState *env)
469 static inline int is_cpu_user (CPUState *env)
479 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
518 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
|
| translate-android.h | 132 register_ret_address(CPUState* env, target_ulong addr)
175 is_ret_address(CPUState* env, target_ulong addr)
|
| op_helper.c | 76 CPUState *saved_env;
101 void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
113 uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
128 void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
135 uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
144 /* FIXME: Pass an axplicit pointer to QF to CPUState, and move saturating
|
| /external/qemu/hw/ |
| apic.c | 67 CPUState *cpu_env;
139 static void apic_local_deliver(CPUState *env, int vector)
170 void apic_deliver_pic_intr(CPUState *env, int level)
279 void cpu_set_apic_base(CPUState *env, uint64_t val)
297 uint64_t cpu_get_apic_base(CPUState *env)
458 void apic_init_reset(CPUState *env)
493 void apic_sipi(CPUState *env)
557 int apic_get_interrupt(CPUState *env)
581 int apic_accept_pic_intr(CPUState *env)
669 CPUState *env
[all...] |
| mips_r4k.c | 74 CPUState *env;
151 CPUState *env = s->env;
168 CPUState *env;
|
| pxa.h | 66 qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
75 CPUState *env, qemu_irq *pic, int lines);
131 CPUState *env;
|
| arm_boot.c | 47 CPUState *env = opaque;
187 void arm_load_kernel(CPUState *env, struct arm_boot_info *info)
|
| android_arm.c | 69 CPUState *env;
|
| pc.c | 129 void cpu_smm_update(CPUState *env)
137 int cpu_get_pic_interrupt(CPUState *env)
158 CPUState *env = first_cpu;
772 CPUState *env = opaque;
851 int cpu_is_bsp(CPUState *env)
890 CPUState *env;
[all...] |
