| /external/llvm/test/MC/ARM/ |
| neon-convert-encoding.s | 3 @ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0x20,0x07,0xfb,0xf3]
4 vcvt.s32.f32 d16, d16
5 @ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xa0,0x07,0xfb,0xf3]
6 vcvt.u32.f32 d16, d16
7 @ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0x20,0x06,0xfb,0xf3]
8 vcvt.f32.s32 d16, d16
9 @ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xa0,0x06,0xfb,0xf3]
10 vcvt.f32.u32 d16, d16
11 @ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0x60,0x07,0xfb,0xf3]
12 vcvt.s32.f32 q8, q
[all...] |
| neont2-convert-encoding.s | 5 @ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x07]
6 vcvt.s32.f32 d16, d16
7 @ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x07]
8 vcvt.u32.f32 d16, d16
9 @ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x06]
10 vcvt.f32.s32 d16, d16
11 @ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x06]
12 vcvt.f32.u32 d16, d16
13 @ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x07]
14 vcvt.s32.f32 q8, q
[all...] |
| neont2-cmp-encoding.s | 5 @ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x07]
6 vcvt.s32.f32 d16, d16
7 @ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x07]
8 vcvt.u32.f32 d16, d16
9 @ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x06]
10 vcvt.f32.s32 d16, d16
11 @ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x06]
12 vcvt.f32.u32 d16, d16
13 @ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x07]
14 vcvt.s32.f32 q8, q
[all...] |
| neon-reciprocal-encoding.s | 7 @ CHECK: vrecpe.f32 d16, d16 @ encoding: [0x20,0x05,0xfb,0xf3]
8 vrecpe.f32 d16, d16
9 @ CHECK: vrecpe.f32 q8, q8 @ encoding: [0x60,0x05,0xfb,0xf3]
10 vrecpe.f32 q8, q8
11 @ CHECK: vrecps.f32 d16, d16, d17 @ encoding: [0xb1,0x0f,0x40,0xf2]
12 vrecps.f32 d16, d16, d17
13 @ CHECK: vrecps.f32 q8, q8, q9 @ encoding: [0xf2,0x0f,0x40,0xf2]
14 vrecps.f32 q8, q8, q9
19 @ CHECK: vrsqrte.f32 d16, d16 @ encoding: [0xa0,0x05,0xfb,0xf3]
20 vrsqrte.f32 d16, d1
[all...] |
| neont2-reciprocal-encoding.s | 9 @ CHECK: vrecpe.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x05]
10 vrecpe.f32 d16, d16
11 @ CHECK: vrecpe.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x05]
12 vrecpe.f32 q8, q8
13 @ CHECK: vrecps.f32 d16, d16, d17 @ encoding: [0x40,0xef,0xb1,0x0f]
14 vrecps.f32 d16, d16, d17
15 @ CHECK: vrecps.f32 q8, q8, q9 @ encoding: [0x40,0xef,0xf2,0x0f]
16 vrecps.f32 q8, q8, q9
21 @ CHECK: vrsqrte.f32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x05]
22 vrsqrte.f32 d16, d1
[all...] |
| vfp4.s | 8 @ ARM: vfma.f32 s2, s4, s0 @ encoding: [0x00,0x1a,0xa2,0xee]
9 @ THUMB: vfma.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x00,0x1a]
10 vfma.f32 s2, s4, s0
12 @ ARM: vfma.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x42,0xf2]
13 @ THUMB: vfma.f32 d16, d18, d17 @ encoding: [0x42,0xef,0xb1,0x0c]
14 vfma.f32 d16, d18, d17
16 @ ARM: vfma.f32 q2, q4, q0 @ encoding: [0x50,0x4c,0x08,0xf2]
17 @ THUMB: vfma.f32 q2, q4, q0 @ encoding: [0x08,0xef,0x50,0x4c]
18 vfma.f32 q2, q4, q0
24 @ ARM: vfnma.f32 s2, s4, s0 @ encoding: [0x40,0x1a,0x92,0xee
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| fmacs.ll | 10 ; VFP2: vmla.f32
13 ; NEON: vmla.f32
16 ; A8: vmul.f32
17 ; A8: vadd.f32
42 ; VFP2: vmla.f32
45 ; NEON: vmla.f32
48 ; A8: vmul.f32
49 ; A8: vadd.f32
60 ; A8: vmul.f32
61 ; A8: vmul.f32
[all...] |
| neon_div.ll | 4 ;CHECK: vrecpe.f32
5 ;CHECK: vrecpe.f32
16 ;CHECK: vrecpe.f32
17 ;CHECK: vrecps.f32
18 ;CHECK: vrecpe.f32
19 ;CHECK: vrecps.f32
30 ;CHECK: vrecpe.f32
31 ;CHECK: vrecps.f32
40 ;CHECK: vrecpe.f32
41 ;CHECK: vrecps.f32
[all...] |
| fabss.ll | 17 ; VFP2: vabs.f32 s1, s1
20 ; NFP1: vabs.f32 d1, d1
22 ; NFP0: vabs.f32 s1, s1
25 ; CORTEXA8: vadd.f32 [[D1:d[0-9]+]]
26 ; CORTEXA8: vabs.f32 {{d[0-9]+}}, [[D1]]
29 ; CORTEXA9: vabs.f32 s{{.}}, s{{.}}
|
| fnegs.ll | 16 ; VFP2: vneg.f32 s{{.*}}, s{{.*}}
19 ; NFP1: vneg.f32 d{{.*}}, d{{.*}}
22 ; NFP0: vneg.f32 s{{.*}}, s{{.*}}
25 ; CORTEXA8: vneg.f32 d{{.*}}, d{{.*}}
28 ; CORTEXA9: vneg.f32 s{{.*}}, s{{.*}}
40 ; VFP2: vneg.f32 s{{.*}}, s{{.*}}
43 ; NFP1: vneg.f32 d{{.*}}, d{{.*}}
46 ; NFP0: vneg.f32 s{{.*}}, s{{.*}}
49 ; CORTEXA8: vneg.f32 d{{.*}}, d{{.*}}
52 ; CORTEXA9: vneg.f32 s{{.*}}, s{{.*}
[all...] |
| fp_convert.ll | 8 ; VFP2: vcvt.s32.f32 s{{.}}, s{{.}}
10 ; NEON: vadd.f32 [[D0:d[0-9]+]]
11 ; NEON: vcvt.s32.f32 d0, [[D0]]
20 ; VFP2: vcvt.u32.f32 s{{.}}, s{{.}}
22 ; NEON: vadd.f32 [[D0:d[0-9]+]]
23 ; NEON: vcvt.u32.f32 d0, [[D0]]
32 ; VFP2: vcvt.f32.u32 s{{.}}, s{{.}}
34 ; NEON: vcvt.f32.u32 d0, d0
43 ; VFP2: vcvt.f32.s32 s{{.}}, s{{.}}
45 ; NEON: vcvt.f32.s32 d0, d
[all...] |
| neon_minmax.ll | 5 ;CHECK: vmin.f32
13 ;CHECK-NOT: vmin.f32
21 ;CHECK: vmin.f32
29 ;CHECK: vmax.f32
37 ;CHECK: vmax.f32
45 ;CHECK-NOT: vmax.f32
53 ;CHECK: vmax.f32
61 ;CHECK: vmax.f32
69 ;CHECK: vmin.f32
77 ;CHECK: vmin.f32
[all...] |
| fadds.ll | 13 ; VFP2: vadd.f32 s0, s1, s0
16 ; NFP1: vadd.f32 d0, d1, d0
18 ; NFP0: vadd.f32 s0, s1, s0
21 ; CORTEXA8: vadd.f32 d0, d1, d0
23 ; CORTEXA9: vadd.f32 s{{.}}, s{{.}}, s{{.}}
|
| fdivs.ll | 13 ; VFP2: vdiv.f32 s0, s1, s0
16 ; NFP1: vdiv.f32 s0, s1, s0
18 ; NFP0: vdiv.f32 s0, s1, s0
21 ; CORTEXA8: vdiv.f32 s0, s1, s0
23 ; CORTEXA9: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
|
| fmuls.ll | 13 ; VFP2: vmul.f32 s0, s1, s0
16 ; NFP1: vmul.f32 d0, d1, d0
18 ; NFP0: vmul.f32 s0, s1, s0
21 ; CORTEXA8: vmul.f32 d0, d1, d0
23 ; CORTEXA9: vmul.f32 s{{.}}, s{{.}}, s{{.}}
|
| /external/llvm/test/CodeGen/Generic/ |
| fpowi-promote.ll | 7 %tmp2339 = call float @llvm.powi.f32( float %tmp23302331, i32 %tmp23282329 )
11 declare float @llvm.powi.f32(float,i32)
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| vfp4.txt | 6 # CHECK: vfma.f32 s2, s4, s0
9 # CHECK: vfma.f32 d16, d18, d17
12 # CHECK: vfma.f32 q2, q4, q0
18 # CHECK: vfnms.f32 s2, s4, s0
24 # CHECK: vfms.f32 s2, s4, s0
27 # CHECK: vfms.f32 d16, d18, d17
30 # CHECK: vfms.f32 q2, q4, q0
36 # CHECK: vfnma.f32 s2, s4, s0
|
| /external/clang/test/CodeGen/ |
| mms-bitfields.c | 4 int f32; member in struct:s1
11 int f32; member in struct:s2
18 int f32; member in struct:s3
|
| ms_struct.c | 5 int f32; member in struct:s1
12 int f32; member in struct:s2
19 int f32; member in struct:s3
|
| /external/llvm/test/CodeGen/X86/ |
| limited-prec.ll | 11 %0 = call float @llvm.exp.f32(float %x) ; <float> [#uses=1]
15 declare float @llvm.exp.f32(float) nounwind readonly
20 %0 = call float @llvm.exp2.f32(float %x) ; <float> [#uses=1]
24 declare float @llvm.exp2.f32(float) nounwind readonly
29 %0 = call float @llvm.pow.f32(float 1.000000e+01, float %x) ; <float> [#uses=1]
33 declare float @llvm.pow.f32(float, float) nounwind readonly
38 %0 = call float @llvm.log.f32(float %x) ; <float> [#uses=1]
42 declare float @llvm.log.f32(float) nounwind readonly
47 %0 = call float @llvm.log2.f32(float %x) ; <float> [#uses=1]
51 declare float @llvm.log2.f32(float) nounwind readonl
[all...] |
| /external/llvm/test/CodeGen/PTX/ |
| aggregates.ll | 8 ; CHECK: ld.param.f32 r[[R0:[0-9]+]], [__param_1];
9 ; CHECK-NEXT: ld.param.f32 r[[R2:[0-9]+]], [__param_3];
10 ; CHECK-NEXT: ld.param.f32 r[[R1:[0-9]+]], [__param_2];
11 ; CHECK-NEXT: ld.param.f32 r[[R3:[0-9]+]], [__param_4];
12 ; CHECK-NEXT: add.rn.f32 r[[R0]], r[[R0]], r[[R2]];
13 ; CHECK-NEXT: add.rn.f32 r[[R1]], r[[R1]], r[[R3]];
|
| llvm-intrinsic.ll | 5 ; CHECK: sqrt.rn.f32 %ret{{[0-9]+}}, %f{{[0-9]+}};
7 %y = call float @llvm.sqrt.f32(float %x)
21 ; CHECK: sin.approx.f32 %ret{{[0-9]+}}, %f{{[0-9]+}};
23 %y = call float @llvm.sin.f32(float %x)
37 ; CHECK: cos.approx.f32 %ret{{[0-9]+}}, %f{{[0-9]+}};
39 %y = call float @llvm.cos.f32(float %x)
51 declare float @llvm.sqrt.f32(float)
53 declare float @llvm.sin.f32(float)
55 declare float @llvm.cos.f32(float)
|
| /external/webkit/Source/WebCore/platform/graphics/filters/arm/ |
| FELightingNEON.cpp | 153 "vmul.f32 " temp##_Q ", " source##_Q ", " source##_Q NL \
154 "vadd.f32 " source##_S3 ", " temp##_S0 ", " temp##_S1 NL \
155 "vadd.f32 " source##_S3 ", " source##_S3 ", " temp##_S2 NL \
156 "vsqrt.f32 " source##_S3 ", " source##_S3 NL
160 "vmul.f32 " destination##_Q ", " source1##_Q ", " source2##_Q NL \
161 "vadd.f32 " destination##_S0 ", " destination##_S0 ", " destination##_S1 NL \
162 "vadd.f32 " destination##_S0 ", " destination##_S0 ", " destination##_S2 NL
166 "vmuleq.f32 " TMP2_S1 ", " DIFFUSE_CONST_S ", " normalVectorLength NL \
167 "vdiveq.f32 " TMP2_S1 ", " TMP2_S1 ", " dotProductLength NL \
168 "vdivne.f32 " TMP2_S1 ", " normalVectorLength ", " dotProductLength N
[all...] |
| /external/qemu/target-arm/ |
| helper.h | 77 DEF_HELPER_3(vfp_adds, f32, f32, f32, env)
79 DEF_HELPER_3(vfp_subs, f32, f32, f32, env)
81 DEF_HELPER_3(vfp_muls, f32, f32, f32, env)
83 DEF_HELPER_3(vfp_divs, f32, f32, f32, env
[all...] |
| /external/llvm/test/CodeGen/XCore/ |
| float-intrinsics.ll | 20 declare float @llvm.cos.f32(float)
25 %result = call float @llvm.cos.f32(float %F)
36 declare float @llvm.exp.f32(float)
41 %result = call float @llvm.exp.f32(float %F)
52 declare float @llvm.exp2.f32(float)
57 %result = call float @llvm.exp2.f32(float %F)
68 declare float @llvm.log.f32(float)
73 %result = call float @llvm.log.f32(float %F)
84 declare float @llvm.log10.f32(float)
89 %result = call float @llvm.log10.f32(float %F
[all...] |
