/external/valgrind/main/none/tests/amd64/ |
insn_pclmulqdq.def | 1 pclmulqdq imm8[0] xmm.uq[0x00017004200ab0cd,0xc000b802f6b31753] xmm.uq[0xa0005c0252074a9a,0x50002e0207b1643c] => 2.uq[0x5ff61cc8b1043fa2,0x00009602d147dc12] 2 pclmulqdq imm8[1] xmm.uq[0x28001701e286710d,0xd4000b81d7f0f773] xmm.uq[0xaa0005c1c2a63aaa,0x550002e1c000dc44] => 2.uq[0xd33d2883021ccb74,0x080804b056c3c3bd] 3 pclmulqdq imm8[16] xmm.uq[0x2a800171beae2d11,0xd54000b9b604d579] xmm.uq[0xaaa0005db1b029ad,0x9550002faf85d3c3] => 2.uq[0x5bd93710a920a9f5,0x777888724b473f64] 4 pclmulqdq imm8[17] xmm.uq[0x8aa80018be70a8d2,0x4554000d3de61358] xmm.uq[0x22aa00077da0c89b,0xd1550004957e233e] => 2.uq[0xd222922d28094790,0x37fb44403e2d3407] 5 pclmulqdq imm8[0] m128.uq[0x68aa8003296cd08e,0x3455400273642736] xmm.uq[0x1a2aa002185fd28a,0x0d155001eadda834] => 2.uq[0x6f56f9abeba01e6c,0x05101111e9709d8f] 6 pclmulqdq imm8[1] m128.uq[0x068aa801d41c9309,0xc3455401c0bc0875] xmm.uq[0xa1a2aa01c70bc327,0x90d15501ca33a080] => 2.uq[0x0c18b0e8ab072480,0x032f76887b10d528] 7 pclmulqdq imm8[16] m128.uq[0x4868aa81c3c78f2f,0xe4345541c8918684] xmm.uq[0x721a2aa1c2f68231,0xf90d1551c8290009] => 2.uq[0x11d8b7b8f72e3644,0x2a080288f207712b] 8 pclmulqdq imm8[17] m128.uq[0xbc868aa9cac23ef5,0x9e434555cc0ede67] xmm.uq[0x8f21a2abccb52e20,0x4790d156c50855ff] => 2.uq[0xd2e5bdd1665023dd,0x240dbdff7a0eb888] 9 pclmulqdq imm8[0] xmm.uq[0xe3c868ac4931e9ec,0x71e434570346b3e5] xmm.uq[0xf8f21a2c685118df,0xbc790d171ad64b5c] => 2.uq[0x0eebfc038c776124,0x5c177a6fb4d9adf2] 10 pclmulqdq imm8[1] xmm.uq[0x5e3c868c6c18e49d,0xef1e43471cba313b] xmm.uq[0xb78f21a4650ad78e,0x5bc790d311332ab6] => (…) [all...] |
insn_ssse3.def | 49 palignr imm8[0] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0xffeeddccbbaa9988] 50 palignr imm8[1] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x34ffeeddccbbaa99] 51 palignr imm8[2] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x1134ffeeddccbbaa] 52 palignr imm8[3] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x221134ffeeddccbb] 53 palignr imm8[4] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x33221134ffeeddcc] 54 palignr imm8[5] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x4433221134ffeedd] 55 palignr imm8[6] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x554433221134ffee] 56 palignr imm8[7] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x66554433221134ff] 57 palignr imm8[8] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x7766554433221134] 58 palignr imm8[9] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x77665544332211 [all...] |
insn_basic.def | 1 adcb eflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[46] 2 adcb eflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[47] 3 adcb eflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[46] 4 adcb eflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[47] 5 adcb eflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[46] 6 adcb eflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[47] 13 adcw eflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3468] 14 adcw eflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3469] 27 adcl eflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654333] 28 adcl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654334 [all...] |
insn_sse2.def | 173 pextrw imm8[0] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[1234] 174 pextrw imm8[1] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[5678] 175 pextrw imm8[2] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[4321] 176 pextrw imm8[3] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[8765] 177 pextrw imm8[4] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[1111] 178 pextrw imm8[5] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[2222] 179 pextrw imm8[6] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[3333] 180 pextrw imm8[7] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[4444] 181 pinsrw imm8[0] r32.ud[0xffffffff] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] => 2.uw[65535,5678,4321,8765,1111,2222,3333,4444] 182 pinsrw imm8[1] r32.ud[0xffffffff] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] => 2.uw[1234,65535,4321,8765 (…) [all...] |
insn_sse.def | 97 pextrw imm8[0] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[1234] 98 pextrw imm8[1] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[5678] 99 pextrw imm8[2] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[4321] 100 pextrw imm8[3] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[8765] 101 pextrw imm8[0] mm.uw[1234,5678,4321,8765] r64.ud[0xffffffff,0xffffffff] => 2.ud[1234,0] 102 pextrw imm8[1] mm.uw[1234,5678,4321,8765] r64.ud[0xffffffff,0xffffffff] => 2.ud[5678,0] 103 pextrw imm8[2] mm.uw[1234,5678,4321,8765] r64.ud[0xffffffff,0xffffffff] => 2.ud[4321,0] 104 pextrw imm8[3] mm.uw[1234,5678,4321,8765] r64.ud[0xffffffff,0xffffffff] => 2.ud[8765,0] 105 pinsrw imm8[0] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[65535,5678,4321,8765] 106 pinsrw imm8[1] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,65535,4321,8765 [all...] |
insn_mmx.def | 72 pslld imm8[4] mm.ud[0x01234567,0x89abcdef] => 1.ud[0x12345670,0x9abcdef0] 75 psllq imm8[4] mm.uq[0x0123456789abcdef] => 1.uq[0x123456789abcdef0] 78 psllw imm8[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] => 1.uw[0x1230,0x5670,0x9ab0,0xdef0] 81 psrad imm8[4] mm.ud[0x01234567,0x89abcdef] => 1.ud[0x00123456,0xf89abcde] 84 psraw imm8[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] => 1.uw[0x0012,0x0456,0xf89a,0xfcde] 87 psrld imm8[4] mm.ud[0x01234567,0x89abcdef] => 1.ud[0x00123456,0x089abcde] 90 psrlq imm8[4] mm.uq[0x0123456789abcdef] => 1.uq[0x00123456789abcde] 93 psrlw imm8[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] => 1.uw[0x0012,0x0456,0x089a,0x0cde]
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pcmpstr64.c | 182 imm8 is the original immediate from the instruction. isSTRM 186 If the given imm8 case can be handled, the return value is True. 195 UInt imm8, Bool isSTRM ) 197 assert(imm8 < 0x80); 201 /* Explicitly reject any imm8 values that haven't been validated, 204 switch (imm8) { 213 UInt fmt = (imm8 >> 0) & 3; // imm8[1:0] data format 214 UInt agg = (imm8 >> 2) & 3; // imm8[3:2] aggregation f [all...] |
/external/valgrind/main/none/tests/x86/ |
insn_ssse3.def | 49 palignr imm8[0] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0xffeeddccbbaa9988] 50 palignr imm8[1] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x34ffeeddccbbaa99] 51 palignr imm8[2] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x1134ffeeddccbbaa] 52 palignr imm8[3] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x221134ffeeddccbb] 53 palignr imm8[4] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x33221134ffeeddcc] 54 palignr imm8[5] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x4433221134ffeedd] 55 palignr imm8[6] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x554433221134ffee] 56 palignr imm8[7] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x66554433221134ff] 57 palignr imm8[8] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x7766554433221134] 58 palignr imm8[9] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x77665544332211 [all...] |
insn_basic.def | 21 adcb eflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[46] 22 adcb eflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[47] 23 adcb eflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[46] 24 adcb eflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[47] 25 adcb eflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[46] 26 adcb eflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[47] 33 adcw eflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3468] 34 adcw eflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3469] 47 adcl eflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654333] 48 adcl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654334 [all...] |
insn_mmxext.def | 6 pextrw imm8[0] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[1234] 7 pextrw imm8[1] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[5678] 8 pextrw imm8[2] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[4321] 9 pextrw imm8[3] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[8765] 10 pinsrw imm8[0] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[65535,5678,4321,8765] 11 pinsrw imm8[1] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,65535,4321,8765] 12 pinsrw imm8[2] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,5678,65535,8765] 13 pinsrw imm8[3] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,5678,4321,65535] 27 pshufw imm8[0x1b] mm.sw[11,22,33,44] mm.sw[0,0,0,0] => 2.sw[44,33,22,11] 28 pshufw imm8[0x1b] m64.sw[11,22,33,44] mm.sw[0,0,0,0] => 2.sw[44,33,22,11 [all...] |
insn_sse2.def | 173 pextrw imm8[0] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[1234] 174 pextrw imm8[1] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[5678] 175 pextrw imm8[2] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[4321] 176 pextrw imm8[3] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[8765] 177 pextrw imm8[4] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[1111] 178 pextrw imm8[5] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[2222] 179 pextrw imm8[6] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[3333] 180 pextrw imm8[7] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[4444] 181 pinsrw imm8[0] r32.ud[0xffffffff] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] => 2.uw[65535,5678,4321,8765,1111,2222,3333,4444] 182 pinsrw imm8[1] r32.ud[0xffffffff] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] => 2.uw[1234,65535,4321,8765 (…) [all...] |
insn_sse.def | 97 pextrw imm8[0] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[1234] 98 pextrw imm8[1] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[5678] 99 pextrw imm8[2] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[4321] 100 pextrw imm8[3] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[8765] 101 pinsrw imm8[0] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[65535,5678,4321,8765] 102 pinsrw imm8[1] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,65535,4321,8765] 103 pinsrw imm8[2] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,5678,65535,8765] 104 pinsrw imm8[3] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,5678,4321,65535] 105 pinsrw imm8[0] m16.uw[0xffff] mm.uw[1234,5678,4321,8765] => 2.uw[65535,5678,4321,8765] 106 pinsrw imm8[1] m16.uw[0xffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,65535,4321,8765 [all...] |
insn_mmx.def | 52 pslld imm8[4] mm.ud[0x01234567,0x89abcdef] => 1.ud[0x12345670,0x9abcdef0] 55 psllq imm8[4] mm.uq[0x0123456789abcdef] => 1.uq[0x123456789abcdef0] 58 psllw imm8[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] => 1.uw[0x1230,0x5670,0x9ab0,0xdef0] 61 psrad imm8[4] mm.ud[0x01234567,0x89abcdef] => 1.ud[0x00123456,0xf89abcde] 64 psraw imm8[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] => 1.uw[0x0012,0x0456,0xf89a,0xfcde] 67 psrld imm8[4] mm.ud[0x01234567,0x89abcdef] => 1.ud[0x00123456,0x089abcde] 70 psrlq imm8[4] mm.uq[0x0123456789abcdef] => 1.uq[0x00123456789abcde] 73 psrlw imm8[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] => 1.uw[0x0012,0x0456,0x089a,0x0cde]
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/external/elfutils/libcpu/defs/ |
i386 | 8 %mask {imm8} 8 104 00001111,10111010,{mod}100{r_m},{imm8}:bt{w} {imm8},{mod}{r_m} 106 00001111,10111010,{mod}111{r_m},{imm8}:btc{w} {imm8},{mod}{r_m} 108 00001111,10111010,{mod}110{r_m},{imm8}:btr{w} {imm8},{mod}{r_m} 110 00001111,10111010,{mod}101{r_m},{imm8}:bts{w} {imm8},{mod}{r_m} 137 `11110010,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpsd {imm8},{Mod}{R_m},{xmmreg [all...] |
/external/llvm/lib/Target/ARM/MCTargetDesc/ |
ARMMCCodeEmitter.cpp | 145 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2' 150 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2' 155 /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2' 225 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand. 755 /// '+/- imm8<<2' operand. 767 // {7-0} = imm8 768 int32_t Imm8 = MI.getOperand(OpIdx).getImm(); 769 bool isAdd = Imm8 >= 0; 772 if (Imm8 < 0) 773 Imm8 = -Imm8 [all...] |
/external/v8/src/ia32/ |
assembler-ia32.cc | 585 void Assembler::mov_b(const Operand& dst, int8_t imm8) { 589 EMIT(imm8); 819 void Assembler::cmpb(const Operand& op, int8_t imm8) { 827 EMIT(imm8); 1040 void Assembler::rcl(Register dst, uint8_t imm8) { 1042 ASSERT(is_uint5(imm8)); // illegal shift count 1043 if (imm8 == 1) { 1049 EMIT(imm8); 1054 void Assembler::rcr(Register dst, uint8_t imm8) { 1056 ASSERT(is_uint5(imm8)); // illegal shift coun 1181 uint8_t imm8 = imm.x_; local [all...] |
assembler-ia32.h | 693 void mov_b(Register dst, int8_t imm8) { mov_b(Operand(dst), imm8); } 694 void mov_b(const Operand& dst, int8_t imm8); 755 void cmpb(Register reg, int8_t imm8) { cmpb(Operand(reg), imm8); } 756 void cmpb(const Operand& op, int8_t imm8); 805 void rcl(Register dst, uint8_t imm8); 806 void rcr(Register dst, uint8_t imm8); 808 void sar(Register dst, uint8_t imm8); 816 void shl(Register dst, uint8_t imm8); [all...] |
disasm-ia32.cc | 583 int imm8 = -1; local 598 imm8 = 1; 600 imm8 = *(data+2); 607 if (imm8 > 0) { 608 AppendToBuffer("%d", imm8); 1200 int8_t imm8 = static_cast<int8_t>(data[1]); local 1210 int8_t imm8 = static_cast<int8_t>(data[1]); local 1220 int8_t imm8 = static_cast<int8_t>(data[1]); local 1230 int8_t imm8 = static_cast<int8_t>(data[1]); local 1293 int8_t imm8 = static_cast<int8_t>(data[1]); local 1314 int8_t imm8 = static_cast<int8_t>(data[1]); local [all...] |
/external/webkit/Source/JavaScriptCore/assembler/ |
SH4Assembler.h | 470 void addlImm8r(int imm8, RegisterID dst) 472 ASSERT((imm8 <= 127) && (imm8 >= -128)); 474 uint16_t opc = getOpcodeGroup3(ADDIMM_OPCODE, dst, imm8); 484 void andlImm8r(int imm8, RegisterID dst) 486 ASSERT((imm8 <= 255) && (imm8 >= 0)); 489 uint16_t opc = getOpcodeGroup5(ANDIMM_OPCODE, imm8); 517 void orlImm8r(int imm8, RegisterID dst) 519 ASSERT((imm8 <= 255) && (imm8 >= 0)) [all...] |
/external/llvm/test/TableGen/ |
TargetInstrInfo.td | 18 def imm8 : RTLNode; 92 def MOV8ri : Inst<(ops R8:$dst, imm8:$src), 94 [(set R8:$dst, imm8:$src)]>;
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/dalvik/vm/compiler/codegen/arm/ |
ArmLIR.h | 452 imm3 rd[11..8] imm8 */ 454 imm3 rd[11..8] imm8 */ 459 kThumb2StrRRI8Predec, /* str(Imm,T4) rd,[rn,#-imm8] [111110000100] 461 kThumb2LdrRRI8Predec, /* ldr(Imm,T4) rd,[rn,#-imm8] [111110000101] 468 [0] imm3[14..12] rd[11..8] imm8[7..0] */ 486 [0] imm3[14..12] rd[11..8] imm8[7..0] */ 488 imm3 rd[11..8] imm8 */ 526 imm3 [1111] imm8[7..0] */ 542 imm8[7..0] */ 565 rd[11..8] imm8 */ [all...] |
/external/llvm/lib/Target/ARM/ |
ARMInstrThumb.td | 210 // t_addrmode_sp := sp + imm8 * 4 224 // t_addrmode_pc := <label> => pc + imm8 * 4 318 // ADD <Rd>, sp, #<imm8> 823 bits<8> imm8; 825 let Inst{7-0} = imm8; 847 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 848 "add", "\t$Rdn, $imm8", 849 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>; 923 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi, 924 "cmp", "\t$Rn, $imm8", [all...] |
/external/llvm/lib/Target/X86/ |
X86InstrFormats.td | 63 def Imm8 : ImmType<1>; 219 : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> { 337 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix. 367 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix. 368 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix. 370 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes. 441 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8. 475 // AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8. 489 // AVX2AIi8 - AVX2 instructions with TA, OpSize prefix and ImmT = Imm8. 593 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix [all...] |
/external/valgrind/main/VEX/priv/ |
guest_generic_x87.c | 695 imm8 is the original immediate from the instruction. isSTRM 699 If the given imm8 case can be handled, the return value is True. 708 UInt imm8, Bool isxSTRM ) 710 vassert(imm8 < 0x80); 714 /* Explicitly reject any imm8 values that haven't been validated, 717 switch (imm8) { 726 UInt fmt = (imm8 >> 0) & 3; // imm8[1:0] data format 727 UInt agg = (imm8 >> 2) & 3; // imm8[3:2] aggregation f [all...] |
host_arm_defs.h | 153 ARMam2_RI=3, /* reg +/- imm8 */ 229 ARMri84_I84=7, /* imm8 `ror` (2 * imm4) */ 239 UShort imm8; member in struct:__anon13304::__anon13305::__anon13306 249 extern ARMRI84* ARMRI84_I84 ( UShort imm8, UShort imm4 ); 284 /* imm8 = abcdefgh, B = NOT(b); 309 UInt imm8; member in struct:__anon13313 313 extern ARMNImm* ARMNImm_TI ( UInt type, UInt imm8 );
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