| /external/llvm/lib/Target/ARM/ |
| Thumb1RegisterInfo.cpp | 100 bool isSub = false;
106 isSub = true;
128 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
133 if (DestReg == ARM::SP || isSub)
173 bool isSub = NumBytes < 0;
175 if (isSub) Bytes = -NumBytes;
189 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
191 } else if (!isSub && BaseReg == ARM::SP) {
211 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
216 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8
[all...] |
| Thumb2InstrInfo.cpp | 182 bool isSub = NumBytes < 0;
183 if (isSub) NumBytes = -NumBytes;
207 if (isSub) {
240 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
248 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
261 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
265 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
394 bool isSub = false;
420 isSub = true;
439 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12
[all...] |
| ARMBaseInstrInfo.cpp | 161 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
169 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
176 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
181 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
187 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
192 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
197 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 410 bool isSub = Opc == sub;
411 return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
444 bool isSub = Opc == sub;
445 return ((int)isSub << 8) | Offset | (IdxMode << 9);
493 bool isSub = Opc == sub;
494 return ((int)isSub << 8) | Offset;
|
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 150 bool isSub = NumBytes < 0;
151 uint64_t Offset = isSub ? -NumBytes : NumBytes;
156 Opc = isSub
167 unsigned Reg = isSub
171 Opc = isSub
175 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
176 if (isSub)
187 StackPtr, false, isSub ? -ThisVal : ThisVal);
195 if (isSub)
[all...] |
| X86ISelDAGToDAG.cpp | [all...] |
| /external/chromium/chrome/browser/safe_browsing/ |
| protocol_parser_unittest.cc | 264 EXPECT_TRUE(entry->IsSub());
271 EXPECT_TRUE(entry->IsSub());
283 EXPECT_TRUE(entry->IsSub());
325 EXPECT_TRUE(entry->IsSub());
[all...] |
| safe_browsing_util.h | 175 bool IsSub() const {
|
| protocol_parser.cc | 437 if (entry->IsSub()) {
|
| safe_browsing_database.cc | 740 DCHECK(!entry->IsSub());
810 DCHECK(entry->IsSub());
[all...] |
| safe_browsing_util.cc | 122 DCHECK(IsSub());
|
| /external/llvm/lib/CodeGen/ |
| AggressiveAntiDepBreaker.cpp | 594 bool IsSub = TRI->isSubRegister(SuperReg, Reg);
595 assert(IsSub && "Expecting group subregister");
596 if (!IsSub)
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombine.h | 357 bool isSub, Instruction &I);
|
| InstCombineAndOrXor.cpp | 335 /// where isSub determines whether the operator is a sub. If we can fold one of
345 ConstantInt *Mask, bool isSub,
385 if (isSub)
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 859 bool isSub = OffImm < 0;
863 if (isSub)
[all...] |
