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  /external/llvm/test/Transforms/InstCombine/
2007-08-02-InfiniteLoop.ll 5 %W = sext i16 %tmp510 to i32 ; <i32> [#uses=1]
6 %X = sext i16 %tmp512 to i32 ; <i32> [#uses=1]
8 %Z = sext i32 %Y to i64 ; <i64> [#uses=1]
bitcast-sext-vector.ll 2 ; CHECK: sext
8 %sext = sext <4 x i1> %cmp to <4 x i8>
9 %val = bitcast <4 x i8> %sext to i32
2006-10-19-SignedToUnsignedCastAndConst-2.ll 3 ; RUN: not grep sext.*i32
6 %Y = sext i8 %SB to i32 ; <i32> [#uses=1]
add-shrink.ll 2 ; RUN: opt < %s -instcombine -S | grep sext | count 1
4 ; Should only have one sext and the add should be i32 instead of i64.
9 %D = sext i32 %B to i64 ; <i64> [#uses=1]
10 %E = sext i32 %C to i64 ; <i64> [#uses=1]
sext.ll 11 %s = sext i32 %t to i64
20 %s = sext i32 %t to i64
29 %s = sext i32 %t to i64
38 %s = sext i32 %t to i64
47 %s = sext i32 %t to i64
56 %s = sext i32 %t to i64
65 %s = sext i32 %u to i64
75 %n = sext i16 %s to i32
88 %t2 = sext i16 %t to i32
109 %b = sext i8 %a to i32
    [all...]
2011-05-02-VectorBoolean.ll 13 %sext = sext <2 x i1> %cmp to <2 x i16>
14 ret <2 x i16> %sext
udiv-simplify-bug-1.ll 7 ; sext instructions should be optimized to zext.
12 %z = sext i32 %r to i64
18 %z = sext i32 %r to i64
udiv-simplify-bug-0.ll 6 %z = sext i32 %r to i64
12 %z = sext i32 %r to i64
2006-02-13-DemandedMiscompile.ll 5 %B = sext i8 %A to i32 ; <i32> [#uses=1]
2007-03-19-BadTruncChangePR1261.ll 5 %A = sext i31 %zzz to i32
vec_sext.ll 6 %sext = sext <4 x i1> %cmp to <4 x i32>
8 %0 = icmp slt <4 x i32> %sext, zeroinitializer
9 %sext3 = sext <4 x i1> %0 to <4 x i32>
  /external/llvm/test/CodeGen/XCore/
sext.ll 4 %2 = sext i1 %1 to i32
8 ; CHECK: sext r0, 1
12 %2 = sext i2 %1 to i32
16 ; CHECK: sext r0, 2
20 %2 = sext i8 %1 to i32
24 ; CHECK: sext r0, 8
28 %2 = sext i16 %1 to i32
32 ; CHECK: sext r0, 16
  /external/llvm/test/CodeGen/X86/
pr3216.ll 15 %bf.val.sext = ashr i8 %1, 5
16 %conv = sext i8 %bf.val.sext to i32
vec_sext.ll 6 %G = sext <4 x i16> %F to <4 x i32>
8 %Y = sext <4 x i16> %H to <4 x i32>
16 %G = sext <4 x i16> %F to <4 x i64>
18 %Y = sext <4 x i16> %H to <4 x i64>
26 %G = sext <4 x i32> %F to <4 x i64>
28 %Y = sext <4 x i32> %H to <4 x i64>
35 %G = sext <4 x i8> %F to <4 x i16>
37 %Y = sext <4 x i8> %H to <4 x i16>
44 %G = sext <4 x i8> %F to <4 x i32>
46 %Y = sext <4 x i8> %H to <4 x i32
    [all...]
avx-sext.ll 7 %B = sext <8 x i16> %A to <8 x i32>
15 %B = sext <4 x i32> %A to <4 x i64>
extmul128.ll 4 %aa = sext i64 %a to i128
5 %bb = sext i64 %b to i128
extmul64.ll 4 %aa = sext i32 %a to i64
5 %bb = sext i32 %b to i64
sext-load.ll 6 %tmp123 = sext i8 %tmp12 to i32 ; <i32> [#uses=1]
  /external/llvm/test/CodeGen/PowerPC/
2007-01-04-ArgExtension.ll 6 %tmp = sext i8 %c to i32 ; <i32> [#uses=1]
7 %tmp1 = sext i16 %s to i32 ; <i32> [#uses=1]
and_sext.ll 7 %tmp.80 = sext i16 %tmp.79 to i32
13 %tmp = sext i16 %X to i32
14 %tmp1 = sext i16 %x to i32
18 %tmp45 = sext i16 %tmp5 to i32
lha.ll 5 %tmp.2 = sext i16 %tmp.1 to i32 ; <i32> [#uses=1]
  /external/llvm/test/CodeGen/Mips/
madd-msub.ll 6 %conv = sext i32 %a to i64
7 %conv2 = sext i32 %b to i64
9 %conv4 = sext i32 %c to i64
28 %conv = sext i32 %a to i64
29 %conv2 = sext i32 %b to i64
38 %conv = sext i32 %c to i64
39 %conv2 = sext i32 %a to i64
40 %conv4 = sext i32 %b to i64
60 %conv = sext i32 %a to i64
61 %conv3 = sext i32 %b to i6
    [all...]
  /external/llvm/test/Transforms/IndVarSimplify/
preserve-signed-wrap.ll 4 ; sext for the addressing, however it shouldn't eliminate the sext
17 ; CHECK: sext i8
18 ; CHECK-NOT: sext
22 %1 = sext i8 %p.01 to i32 ; <i32> [#uses=1]
23 %2 = sext i32 %i.02 to i64 ; <i64> [#uses=1]
  /external/llvm/test/CodeGen/ARM/
fast-isel-crash2.ll 7 %r = sext i4 %t to i32
  /external/llvm/test/CodeGen/Generic/
2005-12-12-ExpandSextInreg.ll 5 %C = sext i8 %B to i64 ; <i64> [#uses=1]

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