| /external/llvm/test/CodeGen/Mips/ |
| 2008-06-05-Carry.ll | 16 ; CHECK: subu
19 ; CHECK: subu
|
| 2008-08-06-Alloca.ll | 5 ; CHECK: subu ${{[0-9]+}}, $sp
6 ; CHECK: subu ${{[0-9]+}}, $sp
|
| alloca.ll | 5 ; CHECK: subu $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]]
8 ; CHECK: subu $[[T2:[0-9]+]], $sp, $[[SZ]]
39 ; CHECK: subu $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]]
|
| /external/kernel-headers/original/asm-mips/ |
| atomic.h | 104 " subu %0, %2 \n"
116 " subu %0, %2 \n"
201 " subu %0, %1, %3 \n"
204 " subu %0, %1, %3 \n"
215 " subu %0, %1, %3 \n"
218 " subu %0, %1, %3 \n"
261 " subu %0, %1, %3 \n"
266 " subu %0, %1, %3 \n"
279 " subu %0, %1, %3 \n"
284 " subu %0, %1, %3 \n
[all...] |
| string.h | 56 "subu\t%2,1\n\t"
114 "subu\t%2,1\n\t"
|
| asm.h | 240 #define REG_SUBU subu
259 #define INT_SUBU subu
296 #define LONG_SUBU subu
343 #define PTR_SUBU subu
|
| local.h | 83 " subu %0, %1, %3 \n"
86 " subu %0, %1, %3 \n"
97 " subu %0, %1, %3 \n"
100 " subu %0, %1, %3 \n"
|
| div64.h | 45 "subu %0, %0, %z6\n\t" \
|
| delay.h | 27 " subu %0, 1 \n"
|
| /external/v8/src/mips/ |
| regexp-macro-assembler-mips.cc | 298 __ Subu(a1, a1, a0); // Length of capture.
336 __ Subu(a3, a3, Operand('a'));
348 __ Subu(current_input_offset(), a2, end_of_input_address());
411 __ Subu(a1, a1, a0); // Length to check.
442 __ Subu(current_input_offset(), a2, end_of_input_address());
497 __ Subu(a0, current_character(), Operand('\t'));
508 __ Subu(a0, current_character(), Operand('\t'));
515 __ Subu(a0, current_character(), Operand('0'));
520 __ Subu(a0, current_character(), Operand('0'));
527 __ Subu(a0, a0, Operand(0x0b))
[all...] |
| /external/libffi/src/mips/ |
| ffitarget.h | 126 # define SUBU subu
133 # define SUBU dsubu
|
| /external/openssl/crypto/bn/asm/ |
| mips.pl | 61 $SUBU="dsubu";
76 $SUBU="subu";
81 $PTR_SUB="subu";
179 subu $a2,4
216 subu $a2,1
231 subu $a2,1
319 subu $a2,4
356 subu $a2,1
367 subu $a2,
[all...] |
| bn-mips.s | 62 subu $6,4
99 subu $6,1
114 subu $6,1
178 subu $6,4
215 subu $6,1
226 subu $6,1
281 subu $6,4
314 subu $6,1
323 subu $6,1
366 subu $7,
[all...] |
| mips-mont.s | 236 subu $24,$10,$24 # tp[i]-np[i]
238 subu $10,$24,$11
246 subu $11,$25,$11 # handle upmost overflow bit
|
| mips-mont.pl | 78 $SUBU="dsubu";
85 $SUBU="subu";
366 $SUBU $lo1,$lo0,$lo1 # tp[i]-np[i]
368 $SUBU $lo0,$lo1,$hi0
376 $SUBU $hi0,$hi1,$hi0 # handle upmost overflow bit
|
| /external/webkit/Source/JavaScriptCore/assembler/ |
| MacroAssemblerMIPS.h | 286 m_assembler.subu(srcDest, MIPSRegisters::zero, srcDest);
340 m_assembler.subu(dest, dest, src);
354 subu dest, src, immTemp
357 m_assembler.subu(dest, dest, immTempRegister);
368 subu dataTemp, dataTemp, immTemp
379 m_assembler.subu(dataTempRegister, dataTempRegister,
389 subu dataTemp, dataTemp, immTemp
403 m_assembler.subu(dataTempRegister, dataTempRegister,
422 subu dataTemp, dataTemp, immTemp
434 m_assembler.subu(dataTempRegister, dataTempRegister, immTempRegister)
[all...] |
| /external/v8/test/cctest/ |
| test-disasm-mips.cc | 116 COMPARE(subu(a0, a1, a2),
117 "00a62023 subu a0, a1, a2");
118 COMPARE(subu(t2, t3, t4),
119 "016c5023 subu t2, t3, t4");
120 COMPARE(subu(v0, v1, s0),
121 "00701023 subu v0, v1, s0");
|
| /bionic/libc/kernel/arch-mips/asm/ |
| asm.h | 94 #define REG_SUBU subu
112 #define INT_SUBU subu
152 #define LONG_SUBU subu
202 #define PTR_SUBU subu
|
| div64.h | 25 #define do_div64_32(res, high, low, base) ({ unsigned long __quot32, __mod32; unsigned long __cf, __tmp, __tmp2, __i; __asm__(".set push\n\t" ".set noat\n\t" ".set noreorder\n\t" "move %2, $0\n\t" "move %3, $0\n\t" "b 1f\n\t" " li %4, 0x21\n" "0:\n\t" "sll $1, %0, 0x1\n\t" "srl %3, %0, 0x1f\n\t" "or %0, $1, %5\n\t" "sll %1, %1, 0x1\n\t" "sll %2, %2, 0x1\n" "1:\n\t" "bnez %3, 2f\n\t" " sltu %5, %0, %z6\n\t" "bnez %5, 3f\n" "2:\n\t" " addiu %4, %4, -1\n\t" "subu %0, %0, %z6\n\t" "addiu %2, %2, 1\n" "3:\n\t" "bnez %4, 0b\n\t" " srl %5, %1, 0x1f\n\t" ".set pop" : "=&r" (__mod32), "=&r" (__tmp), "=&r" (__quot32), "=&r" (__cf), "=&r" (__i), "=&r" (__tmp2) : "Jr" (base), "0" (high), "1" (low)); (res) = __quot32; __mod32; })
|
| /development/ndk/platforms/android-9/arch-mips/include/asm/ |
| asm.h | 94 #define REG_SUBU subu
112 #define INT_SUBU subu
152 #define LONG_SUBU subu
202 #define PTR_SUBU subu
|
| div64.h | 25 #define do_div64_32(res, high, low, base) ({ unsigned long __quot32, __mod32; unsigned long __cf, __tmp, __tmp2, __i; __asm__(".set push\n\t" ".set noat\n\t" ".set noreorder\n\t" "move %2, $0\n\t" "move %3, $0\n\t" "b 1f\n\t" " li %4, 0x21\n" "0:\n\t" "sll $1, %0, 0x1\n\t" "srl %3, %0, 0x1f\n\t" "or %0, $1, %5\n\t" "sll %1, %1, 0x1\n\t" "sll %2, %2, 0x1\n" "1:\n\t" "bnez %3, 2f\n\t" " sltu %5, %0, %z6\n\t" "bnez %5, 3f\n" "2:\n\t" " addiu %4, %4, -1\n\t" "subu %0, %0, %z6\n\t" "addiu %2, %2, 1\n" "3:\n\t" "bnez %4, 0b\n\t" " srl %5, %1, 0x1f\n\t" ".set pop" : "=&r" (__mod32), "=&r" (__tmp), "=&r" (__quot32), "=&r" (__cf), "=&r" (__i), "=&r" (__tmp2) : "Jr" (base), "0" (high), "1" (low)); (res) = __quot32; __mod32; })
|
| /prebuilts/gcc/darwin-x86/mips/mipsel-linux-android-4.4.3/sysroot/usr/include/asm/ |
| asm.h | 94 #define REG_SUBU subu
112 #define INT_SUBU subu
152 #define LONG_SUBU subu
202 #define PTR_SUBU subu
|
| div64.h | 25 #define do_div64_32(res, high, low, base) ({ unsigned long __quot32, __mod32; unsigned long __cf, __tmp, __tmp2, __i; __asm__(".set push\n\t" ".set noat\n\t" ".set noreorder\n\t" "move %2, $0\n\t" "move %3, $0\n\t" "b 1f\n\t" " li %4, 0x21\n" "0:\n\t" "sll $1, %0, 0x1\n\t" "srl %3, %0, 0x1f\n\t" "or %0, $1, %5\n\t" "sll %1, %1, 0x1\n\t" "sll %2, %2, 0x1\n" "1:\n\t" "bnez %3, 2f\n\t" " sltu %5, %0, %z6\n\t" "bnez %5, 3f\n" "2:\n\t" " addiu %4, %4, -1\n\t" "subu %0, %0, %z6\n\t" "addiu %2, %2, 1\n" "3:\n\t" "bnez %4, 0b\n\t" " srl %5, %1, 0x1f\n\t" ".set pop" : "=&r" (__mod32), "=&r" (__tmp), "=&r" (__quot32), "=&r" (__cf), "=&r" (__i), "=&r" (__tmp2) : "Jr" (base), "0" (high), "1" (low)); (res) = __quot32; __mod32; })
|
| /prebuilts/gcc/linux-x86/mips/mipsel-linux-android-4.4.3/sysroot/usr/include/asm/ |
| asm.h | 94 #define REG_SUBU subu
112 #define INT_SUBU subu
152 #define LONG_SUBU subu
202 #define PTR_SUBU subu
|
| div64.h | 25 #define do_div64_32(res, high, low, base) ({ unsigned long __quot32, __mod32; unsigned long __cf, __tmp, __tmp2, __i; __asm__(".set push\n\t" ".set noat\n\t" ".set noreorder\n\t" "move %2, $0\n\t" "move %3, $0\n\t" "b 1f\n\t" " li %4, 0x21\n" "0:\n\t" "sll $1, %0, 0x1\n\t" "srl %3, %0, 0x1f\n\t" "or %0, $1, %5\n\t" "sll %1, %1, 0x1\n\t" "sll %2, %2, 0x1\n" "1:\n\t" "bnez %3, 2f\n\t" " sltu %5, %0, %z6\n\t" "bnez %5, 3f\n" "2:\n\t" " addiu %4, %4, -1\n\t" "subu %0, %0, %z6\n\t" "addiu %2, %2, 1\n" "3:\n\t" "bnez %4, 0b\n\t" " srl %5, %1, 0x1f\n\t" ".set pop" : "=&r" (__mod32), "=&r" (__tmp), "=&r" (__quot32), "=&r" (__cf), "=&r" (__i), "=&r" (__tmp2) : "Jr" (base), "0" (high), "1" (low)); (res) = __quot32; __mod32; })
|
