Lines Matching refs:s4
234 # define SET_REGISTER_AS_OBJECT(_idx, _val) SET_REGISTER(_idx, (s4)_val)
235 # define GET_REGISTER_INT(_idx) ((s4) GET_REGISTER(_idx))
236 # define SET_REGISTER_INT(_idx, _val) SET_REGISTER(_idx, (s4)_val)
260 # define GET_REGISTER_INT(_idx) ((s4)GET_REGISTER(_idx))
261 # define SET_REGISTER_INT(_idx, _val) SET_REGISTER(_idx, (s4)_val)
617 if ((s4) GET_REGISTER(vsrc1) _cmp (s4) GET_REGISTER(vsrc2)) { \
633 if ((s4) GET_REGISTER(vsrc1) _cmp 0) { \
663 s4 firstVal, secondVal, result; \
683 (s4) GET_REGISTER(vsrc1) _op (s4) GET_REGISTER(vsrc2)); \
710 s4 firstVal, result; \
744 s4 firstVal, result; \
762 (s4) GET_REGISTER(vsrc1) _op (s1) vsrc2); \
788 s4 firstVal, secondVal, result; \
807 (s4) GET_REGISTER(vdst) _op (s4) GET_REGISTER(vsrc1)); \
1354 s4 tmp;
1357 tmp = (s4) (INST_B(inst) << 28) >> 28; // sign extend 4-bit value
1358 ILOGV("|const/4 v%d,#0x%02x", vdst, (s4)tmp);
1414 SET_REGISTER_WIDE(vdst, (s4) tmp);
1693 s4 length;
1701 vdst, vsrc1, ref, (s4) GET_REGISTER(vsrc1));
1702 length = (s4) GET_REGISTER(vsrc1);
1739 s4 offset;
1744 offset = FETCH(1) | (((s4) FETCH(2)) << 16);
1806 s4 offset = (s2) FETCH(1); /* sign-extend next code unit */
1822 s4 offset = FETCH(1); /* low-order 16 bits */
1823 offset |= ((s4) FETCH(2)) << 16; /* high-order 16 bits */
1841 s4 offset;
1844 offset = FETCH(1) | (((s4) FETCH(2)) << 16);
1872 s4 offset;
1875 offset = FETCH(1) | (((s4) FETCH(2)) << 16);
2317 float, _FLOAT, s4, _INT)
2331 double, _DOUBLE, s4, _INT)
2388 HANDLE_OP_SHX_INT(OP_SHL_INT, "shl", (s4), <<)
2392 HANDLE_OP_SHX_INT(OP_SHR_INT, "shr", (s4), >>)
2538 HANDLE_OP_SHX_INT_2ADDR(OP_SHL_INT_2ADDR, "shl", (s4), <<)
2542 HANDLE_OP_SHX_INT_2ADDR(OP_SHR_INT_2ADDR, "shr", (s4), >>)
2656 SET_REGISTER(vdst, (s2) vsrc2 - (s4) GET_REGISTER(vsrc1));
2698 SET_REGISTER(vdst, (s1) vsrc2 - (s4) GET_REGISTER(vsrc1));
2728 HANDLE_OP_SHX_INT_LIT8(OP_SHL_INT_LIT8, "shl", (s4), <<)
2732 HANDLE_OP_SHX_INT_LIT8(OP_SHR_INT_LIT8, "shr", (s4), >>)
