Lines Matching full:next
21 // CHECK-NEXT: [[N:%.*]] = alloca i32, align 4
22 // CHECK-NEXT: [[REF:%.*]] = alloca i16*, align 8
23 // CHECK-NEXT: [[S:%.*]] = alloca i16, align 2
24 // CHECK-NEXT: store i8*
25 // CHECK-NEXT: store i32
28 // CHECK-NEXT: [[T0:%.*]] = load i32* [[N]], align 4
29 // CHECK-NEXT: [[DIM0:%.*]] = zext i32 [[T0]] to i64
30 // CHECK-NEXT: [[T0:%.*]] = load i32* [[N]], align 4
31 // CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], 1
32 // CHECK-NEXT: [[DIM1:%.*]] = zext i32 [[T1]] to i64
35 // CHECK-NEXT: [[T0:%.*]] = load i8** [[ARRAY]], align 8
36 // CHECK-NEXT: [[T1:%.*]] = bitcast i8* [[T0]] to i16*
37 // CHECK-NEXT: store i16* [[T1]], i16** [[REF]], align 8
40 // CHECK-NEXT: [[T0:%.*]] = load i16** [[REF]]
41 // CHECK-NEXT: [[T1:%.*]] = mul nsw i64 1, [[DIM1]]
42 // CHECK-NEXT: [[T2:%.*]] = getelementptr inbounds i16* [[T0]], i64 [[T1]]
43 // CHECK-NEXT: [[T3:%.*]] = getelementptr inbounds i16* [[T2]], i64 2
44 // CHECK-NEXT: store i16 3, i16* [[T3]]
47 // CHECK-NEXT: [[T0:%.*]] = load i16** [[REF]]
48 // CHECK-NEXT: [[T1:%.*]] = mul nsw i64 4, [[DIM1]]
49 // CHECK-NEXT: [[T2:%.*]] = getelementptr inbounds i16* [[T0]], i64 [[T1]]
50 // CHECK-NEXT: [[T3:%.*]] = getelementptr inbounds i16* [[T2]], i64 5
51 // CHECK-NEXT: [[T4:%.*]] = load i16* [[T3]]
52 // CHECK-NEXT: store i16 [[T4]], i16* [[S]], align 2
55 // CHECK-NEXT: ret void
