Lines Matching full:kill
204 IntegerReg, /*Kill=*/false);
883 IntReg, /*Kill=*/true,
890 ISD::BITCAST, IntResultReg, /*Kill=*/true);
1157 MaterialReg, /*Kill=*/true);
1181 .addReg(Op0, Op0IsKill * RegState::Kill);
1184 .addReg(Op0, Op0IsKill * RegState::Kill);
1201 .addReg(Op0, Op0IsKill * RegState::Kill)
1202 .addReg(Op1, Op1IsKill * RegState::Kill);
1205 .addReg(Op0, Op0IsKill * RegState::Kill)
1206 .addReg(Op1, Op1IsKill * RegState::Kill);
1223 .addReg(Op0, Op0IsKill * RegState::Kill)
1224 .addReg(Op1, Op1IsKill * RegState::Kill)
1225 .addReg(Op2, Op2IsKill * RegState::Kill);
1228 .addReg(Op0, Op0IsKill * RegState::Kill)
1229 .addReg(Op1, Op1IsKill * RegState::Kill)
1230 .addReg(Op2, Op2IsKill * RegState::Kill);
1246 .addReg(Op0, Op0IsKill * RegState::Kill)
1250 .addReg(Op0, Op0IsKill * RegState::Kill)
1267 .addReg(Op0, Op0IsKill * RegState::Kill)
1272 .addReg(Op0, Op0IsKill * RegState::Kill)
1290 .addReg(Op0, Op0IsKill * RegState::Kill)
1294 .addReg(Op0, Op0IsKill * RegState::Kill)
1312 .addReg(Op0, Op0IsKill * RegState::Kill)
1313 .addReg(Op1, Op1IsKill * RegState::Kill)
1317 .addReg(Op0, Op0IsKill * RegState::Kill)
1318 .addReg(Op1, Op1IsKill * RegState::Kill)
1336 .addReg(Op0, Op0IsKill * RegState::Kill)
1337 .addReg(Op1, Op1IsKill * RegState::Kill)
1341 .addReg(Op0, Op0IsKill * RegState::Kill)
1342 .addReg(Op1, Op1IsKill * RegState::Kill)
