Lines Matching refs:Op1
365 unsigned Op1 = getRegForValue(I->getOperand(1));
366 if (Op1 == 0) return false;
370 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1,
426 unsigned Op1 = getRegForValue(I->getOperand(1));
427 if (Op1 == 0)
437 Op1, Op1IsKill);
1085 unsigned /*Op1*/, bool /*Op1IsKill*/) {
1115 unsigned /*Op1*/, bool /*Op1IsKill*/,
1195 unsigned Op1, bool Op1IsKill) {
1202 .addReg(Op1, Op1IsKill * RegState::Kill);
1206 .addReg(Op1, Op1IsKill * RegState::Kill);
1216 unsigned Op1, bool Op1IsKill,
1224 .addReg(Op1, Op1IsKill * RegState::Kill)
1229 .addReg(Op1, Op1IsKill * RegState::Kill)
1305 unsigned Op1, bool Op1IsKill,
1313 .addReg(Op1, Op1IsKill * RegState::Kill)
1318 .addReg(Op1, Op1IsKill * RegState::Kill)
1329 unsigned Op1, bool Op1IsKill,
1337 .addReg(Op1, Op1IsKill * RegState::Kill)
1342 .addReg(Op1, Op1IsKill * RegState::Kill)
