Lines Matching defs:Result
620 /// this value and returns the result as a ValueVTs value. This uses
645 /// this value and returns the result as a ValueVT value. This uses
1659 // conditional branch to default mbb if the result is greater than the
3277 // Serializing loads here may result in excessive register pressure, and
3585 SDValue Result;
3588 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3595 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3598 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3601 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3606 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3616 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result);
3619 setValue(&I, Result);
3621 // Assign order to result here. If the intrinsic does not produce a result,
3625 AssignOrderingToNode(Result.getNode());
3671 SDValue result;
3679 // final result:
3712 // Add the exponent into the result in integer domain.
3716 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6);
3738 // Add the exponent into the result in integer domain.
3742 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8);
3777 // Add the exponent into the result in integer domain.
3781 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14);
3785 result = DAG.getNode(ISD::FEXP, dl,
3790 setValue(&I, result);
3797 SDValue result;
3830 result = DAG.getNode(ISD::FADD, dl,
3856 result = DAG.getNode(ISD::FADD, dl,
3890 result = DAG.getNode(ISD::FADD, dl,
3895 result = DAG.getNode(ISD::FLOG, dl,
3900 setValue(&I, result);
3907 SDValue result;
3938 result = DAG.getNode(ISD::FADD, dl,
3964 result = DAG.getNode(ISD::FADD, dl,
3999 result = DAG.getNode(ISD::FADD, dl,
4004 result = DAG.getNode(ISD::FLOG2, dl,
4009 setValue(&I, result);
4016 SDValue result;
4049 result = DAG.getNode(ISD::FADD, dl,
4071 result = DAG.getNode(ISD::FADD, dl,
4101 result = DAG.getNode(ISD::FADD, dl,
4106 result = DAG.getNode(ISD::FLOG10, dl,
4111 setValue(&I, result);
4118 SDValue result;
4154 result = DAG.getNode(ISD::BITCAST, dl,
4179 result = DAG.getNode(ISD::BITCAST, dl,
4215 result = DAG.getNode(ISD::BITCAST, dl,
4220 result = DAG.getNode(ISD::FEXP2, dl,
4225 setValue(&I, result);
4232 SDValue result;
4252 // final result:
4287 result = DAG.getNode(ISD::BITCAST, dl,
4312 result = DAG.getNode(ISD::BITCAST, dl,
4348 result = DAG.getNode(ISD::BITCAST, dl,
4353 result = DAG.getNode(ISD::FPOW, dl,
4359 setValue(&I, result);
4403 // If the original was negative, invert the result, producing 1/(x*x*x).
5169 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5170 DAG.setRoot(Result.second);
5368 std::pair<SDValue,SDValue> Result = TLI.LowerCallTo(CLI);
5369 assert((isTailCall || Result.second.getNode()) &&
5371 assert((Result.second.getNode() || !Result.first.getNode()) &&
5373 if (Result.first.getNode()) {
5374 setValue(CS.getInstruction(), Result.first);
5375 } else if (!CanLowerReturn && Result.second.getNode()) {
5376 // The instruction result is the result of loading from the
5398 SDValue L = DAG.getLoad(RetTys[i], getCurDebugLoc(), Result.second, Add,
5415 // Assign order to nodes here. If the call does not produce a result, it won't
5417 if (!Result.second.getNode()) {
5424 DAG.setRoot(Result.second);
5426 AssignOrderingToNode(Result.second.getNode());
5737 /// CallOperand - If this is the result output operand or a clobber
5926 unsigned ResNo = 0; // ResNo - The result number of the next output.
5948 assert(ResNo == 0 && "Asm only has one result!");
6162 // This is the result value of the call.
6334 // If this asm returns a register value, copy the result from that register
6355 // If a result value was tied to an input value, the computed result may
6356 // have a wider width than the expected result. Extract the relevant
6361 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6852 /// directly add them, because expansion might result in multiple MBB's for one
