Lines Matching refs:VT
527 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
531 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
532 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
536 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
537 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
631 /// VT must be a legal type.
632 bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
633 assert(isTypeLegal(VT));
648 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
653 unsigned NumElts = VT.getVectorNumElements();
654 MVT EltTy = VT.getVectorElementType();
709 TargetLowering::findRepresentativeClass(EVT VT) const {
711 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
816 MVT VT = (MVT::SimpleValueType)i;
817 if (isTypeLegal(VT)) continue;
821 EVT EltVT = VT.getVectorElementType();
822 unsigned NElts = VT.getVectorNumElements();
837 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
854 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
866 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
870 EVT NVT = VT.getPow2VectorType();
871 if (NVT == VT) {
874 unsigned NumElts = VT.getVectorNumElements();
875 ValueTypeActions.setTypeAction(VT,
879 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
901 EVT TargetLowering::getSetCCResultType(EVT VT) const {
902 assert(!VT.isVector() && "No default SetCC type for vectors!");
915 /// This method returns the number of registers needed, and the VT for each
916 /// register. It also returns the VT and quantity of the intermediate values
919 unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
923 unsigned NumElts = VT.getVectorNumElements();
930 LegalizeTypeAction TA = getTypeAction(Context, VT);
932 RegisterVT = getTypeToTransformTo(Context, VT);
941 EVT EltTy = VT.getVectorElementType();
996 EVT VT = ValueVTs[j];
1008 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1010 if (VT.bitsLT(MinVT))
1011 VT = MinVT;
1014 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1015 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1123 EVT VT = Op.getValueType();
1124 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
1127 VT));
1138 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1351 EVT VT = Op.getValueType();
1352 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
1353 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1366 EVT VT = Op.getValueType();
1367 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
1368 TLO.DAG.getConstant(Expanded, VT));
1442 EVT VT = Op.getValueType();
1443 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1481 EVT VT = Op.getValueType();
1483 unsigned VTSize = VT.getSizeInBits();
1506 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1534 EVT VT = Op.getValueType();
1547 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
1562 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1769 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1771 VT.getSizeInBits());
1905 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1914 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1916 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1922 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1947 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1970 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
2007 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
2061 return DAG.getSetCC(dl, VT,
2081 case ISD::SETEQ: return DAG.getConstant(0, VT);
2084 case ISD::SETNE: return DAG.getConstant(1, VT);
2088 return DAG.getConstant(C1.isNegative(), VT);
2092 return DAG.getConstant(C1.isNonNegative(), VT);
2110 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2128 return DAG.getConstant(Cond == ISD::SETNE, VT);
2142 return DAG.getSetCC(dl, VT, ZextOp,
2152 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
2155 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
2160 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
2188 return DAG.getSetCC(dl, VT, Val, N1,
2192 (VT == MVT::i1 ||
2203 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2209 if (Op0.getValueType().bitsGT(VT))
2210 Op0 = DAG.getNode(ISD::AND, dl, VT,
2211 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2212 DAG.getConstant(1, VT));
2213 else if (Op0.getValueType().bitsLT(VT))
2214 Op0 = DAG.getNode(ISD::AND, dl, VT,
2215 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2216 DAG.getConstant(1, VT));
2218 return DAG.getSetCC(dl, VT, Op0,
2237 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2239 return DAG.getSetCC(dl, VT, N0,
2245 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2247 return DAG.getSetCC(dl, VT, N0,
2253 return DAG.getConstant(0, VT); // X < MIN --> false
2255 return DAG.getConstant(1, VT); // X >= MIN --> true
2257 return DAG.getConstant(0, VT); // X > MAX --> false
2259 return DAG.getConstant(1, VT); // X <= MAX --> true
2263 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2266 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2270 return DAG.getSetCC(dl, VT, N0,
2275 return DAG.getSetCC(dl, VT, N0,
2285 return DAG.getSetCC(dl, VT, N0,
2295 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2300 (VT == N0.getValueType() ||
2301 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2310 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2318 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2341 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
2369 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
2377 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
2387 return DAG.getConstant(0, VT);
2389 return DAG.getConstant(1, VT);
2391 return DAG.getUNDEF(VT);
2400 return DAG.getSetCC(dl, VT, N0, N0, Cond);
2412 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2415 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2418 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2421 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2425 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2428 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2431 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2434 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2456 return DAG.getConstant(EqVal, VT);
2460 return DAG.getConstant(EqVal, VT);
2462 return DAG.getConstant(EqVal, VT);
2468 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
2478 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
2480 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
2484 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2487 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2500 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2512 DAG.getSetCC(dl, VT, N0.getOperand(0),
2523 DAG.getSetCC(dl, VT, N0.getOperand(1),
2542 return DAG.getSetCC(dl, VT, N0.getOperand(1),
2546 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2555 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2565 return DAG.getSetCC(dl, VT, N1.getOperand(1),
2569 return DAG.getSetCC(dl, VT, N1.getOperand(0),
2578 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
2592 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2600 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2646 if (VT != MVT::i1) {
2650 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2820 EVT VT) const {
3323 EVT VT = N->getValueType(0);
3328 if (!isTypeLegal(VT))
3337 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
3338 isOperationLegalOrCustom(ISD::MULHS, VT))
3339 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
3340 DAG.getConstant(magics.m, VT));
3341 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
3342 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
3343 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
3345 DAG.getConstant(magics.m, VT)).getNode(), 1);
3350 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
3356 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
3362 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
3369 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
3373 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
3383 EVT VT = N->getValueType(0);
3388 if (!isTypeLegal(VT))
3402 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
3414 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
3415 isOperationLegalOrCustom(ISD::MULHU, VT))
3416 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
3417 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
3418 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
3419 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
3420 DAG.getConstant(magics.m, VT)).getNode(), 1);
3429 return DAG.getNode(ISD::SRL, dl, VT, Q,
3432 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
3435 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
3439 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
3442 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
