Lines Matching defs:SR
573 SetVector<const CodeGenRegister*> SR;
574 Reg->addSubRegsPreOrder(SR, RegBank);
575 diffEncode(SubRegLists[i], Reg->EnumValue, SR.begin(), SR.end());
580 for (unsigned j = 0, je = SR.size(); j != je; ++j)
581 SRIs.push_back(Reg->getSubRegIndex(SR[j]));
