Lines Matching refs:due
22 0x0F any All loads delayed due to store blocks
25 0x02 walk_completed Counts number of completed page walks due to load miss in the STLB
29 0x80 large_walk_completed Counts number of completed large page walks due to load miss in the STLB
160 0x80 large_walk_completed Counts number of completed large page walks due to misses in the STLB
175 0x04 m_evict Counts the number of modified lines evicted from the L1 data cache due to replacement
176 0x08 m_snoop_evict Counts the number of modified lines evicted from the L1 data cache due to snoop HITM intervention
189 0x04 cycles_stalled Cycle counts for which an instruction fetch stalls due to a L1I cache miss, ITLB miss or ITLB fault
203 0x80 large_walk_completed Counts number of completed large page walks due to misses in the STLB
205 0x01 lcp Cycles Instruction Length Decoder stalls due to length changing prefixes: 66, 67 or REX
206 0x02 mru Instruction Length Decoder stall cycles due to Brand Prediction Unit (PBU) Most Recently Used (MRU) bypass
207 0x04 iq_full Stall cycles due to a full instruction queue
234 0x02 load Counts the cycles of stall due to lack of load buffer for load operation
236 0x08 store This event counts the number of cycles that a resource related stall will occur due to the number of store instructions reaching the limit of the pipeline, (i
237 0x10 rob_full Counts the cycles of stall due to reorder buffer full
238 0x20 fpcw Counts the number of cycles while execution was stalled due to writing the floating-point unit (FPU) control word
239 0x40 mxcsr Stalls due to the MXCSR register rename occurring to close to a previous MXCSR rename
240 0x80 other Counts the number of cycles while execution was stalled due to other resource issues
279 0x02 mem_order Counts the number of machine clears due to memory order conflicts
315 0x01 flags Counts the number of cycles during which execution stalled due to several reasons, one of which is a partial flag register stall
318 0x08 scoreboard Counts the cycles where we stall due to microarchitecturally required serialization
319 0x0F any Counts all Register Allocation Table stall cycles due to: Cycles when ROB read port stalls occurred, which did not allow new micro-ops to enter the execution pipe
322 0x02 bad_target Counts number of Branch Address Calculator clears (BACLEAR) asserted due to conditional branch instructions in which there was a target hit but the direction was wrong
325 0x02 late Counts late Branch Prediction Unit clears due to Most Recently Used conflicts
328 0x01 load Counts L2 load operations due to HW prefetch or demand loads
329 0x02 rfo Counts L2 RFO operations due to HW prefetch or demand RFOs
330 0x04 ifetch Counts L2 instruction fetch operations due to HW prefetch or demand ifetch
333 0x20 fill Counts L2 cache line fill operations due to load, RFO, L1D writeback or prefetch
357 0x08 fill_dropped Counts the number of SQ L2 fills dropped due to L2 busy
