Lines Matching refs:cp15
54 env->cp15.c0_cpuid = id;
61 env->cp15.c0_cachetype = 0x1dd20d2;
62 env->cp15.c1_sys = 0x00090078;
68 env->cp15.c0_cachetype = 0x0f004006;
69 env->cp15.c1_sys = 0x00000078;
77 env->cp15.c0_cachetype = 0x1dd20d2;
78 env->cp15.c1_sys = 0x00090078;
90 memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
91 memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
92 env->cp15.c0_cachetype = 0x1dd20d2;
93 env->cp15.c1_sys = 0x00050078;
105 memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
106 memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
107 env->cp15.c0_cachetype = 0x1dd20d2;
125 memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
126 memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
127 env->cp15.c0_cachetype = 0x82048004;
128 env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
129 env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
130 env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
131 env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
132 env->cp15.c1_sys = 0x00c50078;
150 memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
151 memcpy(env->cp15.c0_c2, cortexa8r2_cp15_c0_c2, 8 * sizeof(uint32_t));
152 env->cp15.c0_cachetype = 0x82048004;
153 env->cp15.c0_clid = (1 << 27) | (2 << 24) | (4 << 3) | 3;
154 env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
155 env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
156 env->cp15.c0_ccsid[2] = 0xf03fe03a; /* 256k L2 cache. */
157 env->cp15.c1_sys = 0x00c50078;
181 memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
182 memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t));
183 env->cp15.c0_cachetype = 0x80038003;
184 env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
185 env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
186 env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
187 env->cp15.c1_sys = 0x00c50078;
217 env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
218 env->cp15.c0_cachetype = 0x5109149;
219 env->cp15.c1_sys = 0x00000070;
220 env->cp15.c15_i_max = 0x000;
221 env->cp15.c15_i_min = 0xff0;
232 env->cp15.c0_cachetype = 0xd172172;
233 env->cp15.c1_sys = 0x00000078;
247 env->cp15.c0_cachetype = 0xd172172;
248 env->cp15.c1_sys = 0x00000078;
253 env->cp15.c1_sys = 0x00000070;
270 id = env->cp15.c0_cpuid;
283 env->cp15.c15_cpar = 3;
285 env->cp15.c15_cpar = 1;
311 env->cp15.c2_base_mask = 0xffffc000u;
392 env->cp15.c0_cpuid = id;
586 env->cp15.c6_insn = address;
589 env->cp15.c6_data = address;
597 cpu_abort(env, "cp15 insn %08x\n", insn);
602 cpu_abort(env, "cp15 insn %08x\n", insn);
919 env->cp15.c1_secfg &= ~1;
933 addr += env->cp15.c12_mvbar;
935 if (env->cp15.c1_sys & (1 << 13)) {
938 addr += env->cp15.c12_vbar;
943 if (env->cp15.c1_sys & (1 << 13)) {
957 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
984 switch ((env->cp15.c1_sys >> 8) & 3) {
1020 if (address & env->cp15.c2_mask)
1021 table = env->cp15.c2_base1 & 0xffffc000;
1023 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
1046 domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3;
1152 domain = (env->cp15.c3 >> domain) & 3;
1205 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
1234 base = env->cp15.c6_region[n];
1248 mask = env->cp15.c5_insn;
1250 mask = env->cp15.c5_data;
1300 address += env->cp15.c13_fcse;
1302 if ((env->cp15.c1_sys & 1) == 0) {
1312 } else if (env->cp15.c1_sys & (1 << 23)) {
1341 env->cp15.c5_insn = ret;
1342 env->cp15.c6_insn = address;
1345 env->cp15.c5_data = ret;
1347 env->cp15.c5_data |= (1 << 11);
1348 env->cp15.c6_data = address;
1417 env->cp15.c0_cssel = val & 0xf;
1429 env->cp15.c1_sys = val;
1436 env->cp15.c1_xscaleauxcr = val;
1444 if (env->cp15.c1_coproc != val) {
1445 env->cp15.c1_coproc = val;
1460 if (env->cp15.c1_secfg & 1)
1462 env->cp15.c1_secfg = val;
1465 if (env->cp15.c1_secfg & 1)
1467 env->cp15.c1_sedbg = val;
1470 if (env->cp15.c1_secfg & 1)
1472 env->cp15.c1_nseac = val;
1486 env->cp15.c2_data = val;
1489 env->cp15.c2_insn = val;
1497 env->cp15.c2_base0 = val;
1500 env->cp15.c2_base1 = val;
1504 env->cp15.c2_control = val;
1505 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
1506 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val);
1514 env->cp15.c3 = val;
1526 env->cp15.c5_data = val;
1531 env->cp15.c5_insn = val;
1536 env->cp15.c5_data = val;
1541 env->cp15.c5_insn = val;
1551 env->cp15.c6_region[crm] = val;
1557 env->cp15.c6_data = val;
1561 env->cp15.c6_insn = val;
1569 env->cp15.c15_i_max = 0x000;
1570 env->cp15.c15_i_min = 0xff0;
1579 env->cp15.c7_par = val & 0xfffff6ff;
1581 env->cp15.c7_par = val & 0xfffff1ff;
1601 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
1603 env->cp15.c7_par = phys_addr & 0xfffff000;
1606 env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
1645 env->cp15.c9_data = val;
1648 env->cp15.c9_insn = val;
1676 env->cp15.c9_pmcr_data = val;
1714 env->cp15.c9_useren = val & 1;
1720 env->cp15.c9_inten |= val & 0xf;
1726 env->cp15.c9_inten &= ~(val & 0xf);
1749 env->cp15.c12_vbar = val & ~0x1f;
1755 if (!(env->cp15.c1_secfg & 1)) {
1756 env->cp15.c12_mvbar = val & ~0x1f;
1771 if (env->cp15.c13_fcse != val)
1773 env->cp15.c13_fcse = val;
1777 if (env->cp15.c13_context != val
1780 env->cp15.c13_context = val;
1791 if (env->cp15.c15_cpar != (val & 0x3fff)) {
1794 env->cp15.c15_cpar = val & 0x3fff;
1805 env->cp15.c15_ticonfig = val & 0xe7;
1806 env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */
1810 env->cp15.c15_i_max = val;
1813 env->cp15.c15_i_min = val;
1816 env->cp15.c15_threadid = val & 0xffff;
1830 cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1851 return env->cp15.c0_cpuid;
1853 return env->cp15.c0_cachetype;
1886 return env->cp15.c0_c1[op2];
1890 return env->cp15.c0_c2[op2];
1909 return env->cp15.c0_ccsid[env->cp15.c0_cssel];
1911 return env->cp15.c0_clid;
1919 return env->cp15.c0_cssel;
1931 return env->cp15.c1_sys;
1934 return env->cp15.c1_xscaleauxcr;
1957 return env->cp15.c1_coproc;
1968 if (env->cp15.c1_secfg & 1)
1970 return env->cp15.c1_secfg;
1972 if (env->cp15.c1_secfg & 1)
1974 return env->cp15.c1_sedbg;
1976 return env->cp15.c1_nseac;
1989 return env->cp15.c2_data;
1992 return env->cp15.c2_insn;
2000 return env->cp15.c2_base0;
2002 return env->cp15.c2_base1;
2004 return env->cp15.c2_control;
2010 return env->cp15.c3;
2019 return simple_mpu_ap_bits(env->cp15.c5_data);
2020 return env->cp15.c5_data;
2023 return simple_mpu_ap_bits(env->cp15.c5_data);
2024 return env->cp15.c5_insn;
2028 return env->cp15.c5_data;
2032 return env->cp15.c5_insn;
2040 return env->cp15.c6_region[crm];
2046 return env->cp15.c6_data;
2055 return env->cp15.c6_insn;
2059 return env->cp15.c6_insn;
2068 return env->cp15.c7_par;
2084 return env->cp15.c9_data;
2086 return env->cp15.c9_insn;
2094 return env->cp15.c9_pmcr_data;
2103 return env->cp15.c9_useren;
2109 return env->cp15.c9_inten;
2138 return env->cp15.c12_vbar;
2143 return env->cp15.c12_mvbar;
2154 return env->cp15.c13_fcse;
2156 return env->cp15.c13_context;
2165 return env->cp15.c15_cpar;
2174 return env->cp15.c15_ticonfig;
2176 return env->cp15.c15_i_max;
2178 return env->cp15.c15_i_min;
2180 return env->cp15.c15_threadid;
2194 cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
