Lines Matching refs:x1F
53 OPC_SPECIAL3 = (0x1F << 26),
152 OPC_DDIVU = 0x1F | OPC_SPECIAL,
206 #define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6))
226 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
243 OPC_SYNCI = (0x1F << 16) | OPC_REGIMM,
285 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
294 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
302 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
316 OPC_C0_LAST = (0x1F << 21) | OPC_CP0,
341 OPC_DERET = 0x1F | OPC_C0,
346 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
389 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
517 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
1410 target_ulong uimm = ((uint16_t)imm) & 0x1f;
1434 switch ((ctx->opcode >> 21) & 0x1f) {
1484 switch ((ctx->opcode >> 21) & 0x1f) {
1518 switch ((ctx->opcode >> 21) & 0x1f) {
1874 tcg_gen_andi_tl(t0, t0, 0x1f);
1881 tcg_gen_andi_tl(t0, t0, 0x1f);
1886 switch ((ctx->opcode >> 6) & 0x1f) {
1889 tcg_gen_andi_tl(t0, t0, 0x1f);
1902 tcg_gen_andi_i32(t2, t2, 0x1f);
1910 tcg_gen_andi_tl(t0, t0, 0x1f);
1934 switch ((ctx->opcode >> 6) & 0x1f) {
6016 switch (ctx->opcode & FOP(0x3f, 0x1f)) {
7657 rs = (ctx->opcode >> 21) & 0x1f;
7658 rt = (ctx->opcode >> 16) & 0x1f;
7659 rd = (ctx->opcode >> 11) & 0x1f;
7660 sa = (ctx->opcode >> 6) & 0x1f;
