Lines Matching full:misses
42 I1 cache read misses (<computeroutput>I1mr</computeroutput>) and
43 LL cache instruction read misses (<computeroutput>ILmr</computeroutput>).
49 D1 cache read misses (<computeroutput>D1mr</computeroutput>), and
50 LL cache data read misses (<computeroutput>DLmr</computeroutput>).
56 D1 cache write misses (<computeroutput>D1mw</computeroutput>), and
57 LL cache data write misses (<computeroutput>DLmw</computeroutput>).
132 ==31751== I1 misses: 276
133 ==31751== LLi misses: 275
138 ==31751== D1 misses: 41,185 ( 21,905 rd + 19,280 wr)
139 ==31751== LLd misses: 23,085 ( 3,987 rd + 19,098 wr)
143 ==31751== LL misses: 23,360 ( 4,262 rd + 19,098 wr)
149 right), the number of I1 misses, and the number of LL instruction
150 (<computeroutput>LLi</computeroutput>) misses.</para>
161 number of memory accesses, not the number of L1 misses. I.e. it is
703 write misses.</para>
762 write misses.</para>
926 example, I cache misses (<option>--show=I1mr,ILmr</option>), or data
927 read misses (<option>--show=D1mr,DLmr</option>), or LL data misses
958 each function that covers more than 1% of LL read misses or 1% of LL
959 write misses, use this option:</para>
1093 After that, we have found that LL misses are typically a much bigger source
1094 of slow-downs than L1 misses. So it's worth looking for any snippets of
1107 <computeroutput>Bim</computeroutput> misses can also be helpful.
1108 In particular, <computeroutput>Bim</computeroutput> misses are often caused
1234 <para>If one block hits, the other misses --> counted
1337 <para>It doesn't account for cache misses not visible at the
1338 instruction level, e.g. those arising from TLB misses, or
