Lines Matching refs:instruction
53 /* test macros to generate and output the result of a single instruction */
62 #define TESTINSN_vmovf32_imm(instruction, DD, imm) \
67 instruction ", #"#imm"\n\t"\
74 instruction, out[0]); \
77 #define TESTINSN_vmov_core_single(instruction, RN, SD, SDval) \
85 instruction "\n\t" \
92 instruction, out[0]); \
95 #define TESTINSN_vmov_single_core(instruction, SD, RN, RNval) \
103 instruction "\n\t"\
110 instruction, out[0]); \
113 #define TESTINSN_vmov_2core_2single(instruction, RD1, RD2, SN, SM, SNval, SMval) \
123 instruction "\n\t"\
131 instruction, out[0], out[1]); \
134 #define TESTINSN_vmov_2single_2core(instruction, SD1, SD2, RN, RM, RNval, RMval) \
144 instruction "\n\t"\
151 instruction, out[0], out[1]); \
154 #define TESTINSN_vmov_double_2core(instruction, DD, RN, RM, RNval, RMval) \
163 instruction "\n\t"\
170 instruction, out[0], out[1]); \
173 #define TESTINSN_vmov_2core_double(instruction, RD1, RD2, DN, DNval0, DNval1) \
182 instruction "\n\t" \
190 instruction, out[0], out[1]); \
193 #define TESTINSN_un_f64(instruction, DD, DM, DMtype, DMval0, DMval1) \
200 instruction "\n\t" \
207 instruction, out[1], out[0], DMval1, DMval0); \
210 #define TESTINSN_un_f32(instruction, SD, SM, SMtype, SMval) \
217 instruction "\n\t" \
224 instruction, out[0], SMval); \
227 #define TESTINSN_un_cvt_ds(instruction, DD, SM, SMval) \
234 instruction "\n\t" \
241 instruction, out[1], out[0], SMval); \
244 #define TESTINSN_un_cvt_sd(instruction, SD, DM, DMval0, DMval1) \
251 instruction "\n\t" \
258 instruction, out[0], DMval1, DMval0); \
261 #define TESTINSN_cvt_i32_f64(instruction, SD, DM, DMval0, DMval1) \
268 instruction "\n\t" \
275 instruction, out[0], DMval1, DMval0); \
278 #define TESTINSN_cvt_f64_i32(instruction, DD, SM, SMval) \
285 instruction "\n\t" \
292 instruction, out[0], out[1], SMval); \
295 #define TESTINSN_un_f64_q_vmrs(instruction, DD, DM, DMtype, DMval, RN) \
305 instruction "\n\t" \
314 instruction, out[1], out[0], DMval, fpscr); \
317 #define TESTINSN_core_to_scalar(instruction, DD, DM, DMval) \
324 instruction "\n\t" \
331 instruction, out[1], out[0], DMval); \
334 #define TESTINSN_vldr_f64(instruction, DD, RN, RNval, imm) \
341 instruction "\n\t" \
348 instruction, out[1], out[0], *(int*) (RNval + imm)); \
351 #define TESTINSN_vldr_f32(instruction, SD, RN, RNval, imm) \
358 instruction "\n\t" \
365 instruction, out[0], *(int*) (RNval + imm)); \
368 #define TESTINSN_vstr64(instruction, DD, DDval, RM, RMval, imm) \
380 instruction "\n\t" \
387 instruction, out[1], out[0], *(int*) (RMval + imm)); \
390 #define TESTINSN_vstr32(instruction, SD, RM, RMval, imm) \
399 instruction "\n\t" \
406 instruction, out[0], *(int*) (RMval + imm)); \
409 #define TESTINSN_scalar_to_core(instruction, QD, QM, QMtype, QMval) \
416 instruction "\n\t" \
423 instruction, out[0], QMval); \
426 #define TESTINSN_VLDn(instruction, QD1, QD2, QD3, QD4) \
435 instruction ", [%1]\n\t" \
448 instruction, out[0], out[1], out[2], out[3], out[4],\
452 #define TESTINSN_VSTMIAnoWB(instruction, RN, QD, QDval) \
459 instruction "\n\t" \
465 instruction, out[0], out[1]); \
468 #define TESTINSN_VSTMIAnoWB32(instruction, RN, SD, SDval) \
475 instruction "\n\t" \
481 instruction, out[0]); \
541 #define TESTINSN_VLDMIAnoWB(instruction, RN, QD) \
549 instruction "\n\t" \
557 instruction, out[0], out[1], out[2], out[3]); \
605 instruction, dD, rN, rNval, offset) \
612 instruction ", #" #offset "]\n\t" \
619 instruction, out[1], out[0], rNval); \
680 #define TESTINSN_VSTn(instruction, QD1, QD2, QD3, QD4) \
692 instruction ", [%0]\n\t" \
699 instruction, out[0], out[1], out[2], out[3], out[4],\
703 #define TESTINSN_bin(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \
711 instruction "\n\t" \
719 instruction, out[1], out[0], QMval, QNval); \
722 #define TESTINSN_bin_f64(instruction, QD, QM, QMtype, QMval0, QMval1, QN, QNtype, QNval0, QNval1) \
730 instruction "\n\t" \
738 instruction, out[1], out[0], QMval1, QMval0, QNval1, QNval0); \
741 #define TESTINSN_bin_f32(instruction, SD, SM, SMtype, SMval, SN, SNtype, SNval) \
749 instruction "\n\t" \
757 instruction, out[0], SMval, SNval); \
760 #define TESTINSN_cmp_f64(instruction, DD, DDval0, DDval1, DM, DMval0, DMval1) \
769 instruction "\n\t" \
778 instruction, out[0] & 0xffffff60, DDval1, DDval0, DMval1, DMval0); \
781 #define TESTINSN_cmp_f32(instruction, SD, SDval, SM, SMval) \
790 instruction "\n\t" \
799 instruction, (out[0] & 0xf0000000) >> 28, SDval, SMval); \
802 #define TESTINSN_cmpz_f32(instruction, SD, SDval) \
808 instruction ", #0\n\t" \
817 instruction, out[0] & 0xffffff60, SDval); \
820 #define TESTINSN_cmpz_f64(instruction, DD, DDval0, DDval1) \
826 instruction ", #0\n\t" \
834 instruction, out[0] & 0xffffff60, DDval1, DDval0); \
