Lines Matching refs:ud
47 adcl eflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654333]
48 adcl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654334]
49 adcl eflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[99999999]
50 adcl eflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[100000000]
51 adcl eflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[99999999]
52 adcl eflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[100000000]
53 adcl eflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[99999999]
54 adcl eflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[100000000]
55 adcl eflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
56 adcl eflags[0x1,0x1] : r32.ud[12345678] r32.ud[87654321] => 1.ud[100000000]
57 adcl eflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[99999999]
58 adcl eflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[100000000]
59 adcl eflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
60 adcl eflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[100000000]
74 addl imm8[12] r32.ud[87654321] => 1.ud[87654333]
75 addl imm32[12345678] eax.ud[87654321] => 1.ud[99999999]
76 addl imm32[12345678] ebx.ud[87654321] => 1.ud[99999999]
77 addl imm32[12345678] m32.ud[87654321] => 1.ud[99999999]
78 addl r32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
79 addl r32.ud[12345678] m32.ud[87654321] => 1.ud[99999999]
80 addl m32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
94 andl imm8[0x31] r32.ud[0x12345678] => 1.ud[0x00000030]
95 andl imm32[0x86427531] eax.ud[0x12345678] => 1.ud[0x02005430]
96 andl imm32[0x86427531] ebx.ud[0x12345678] => 1.ud[0x02005430]
97 andl imm32[0x86427531] m32.ud[0x12345678] => 1.ud[0x02005430]
98 andl r32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x02005430]
99 andl r32.ud[0x86427531] m32.ud[0x12345678] => 1.ud[0x02005430]
100 andl m32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x02005430]
103 bsfl r32.ud[0x13572468] r32.ud[0] => 1.ud[3]
104 bsfl m32.ud[0x75318642] r32.ud[0] => 1.ud[1]
107 bsrl r32.ud[0x13572468] r32.ud[0] => 1.ud[28]
108 bsrl m32.ud[0x75318642] r32.ud[0] => 1.ud[30]
109 bswapl r32.ud[0x12345678] => 0.ud[0x78563412]
118 btl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
119 btl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
120 btl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
121 btl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
122 btl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
123 btl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
124 btl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
125 btl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
134 btcl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
135 btcl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
136 btcl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
137 btcl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
138 btcl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
139 btcl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
140 btcl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
141 btcl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
150 btrl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
151 btrl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
152 btrl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
153 btrl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
154 btrl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
155 btrl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
156 btrl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
157 btrl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
166 btsl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
167 btsl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
168 btsl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
169 btsl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
170 btsl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
171 btsl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
172 btsl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
173 btsl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
176 cdq eax.ud[0x12345678] : => edx.ud[0x00000000] eax.ud[0x12345678]
177 cdq eax.ud[0xfedcba98] : => edx.ud[0xffffffff] eax.ud[0xfedcba98]
324 cmpl imm8[3] r32.ud[2] => eflags[0x010,0x010]
325 cmpl imm8[2] r32.ud[3] => eflags[0x010,0x000]
326 cmpl imm8[12] r32.ud[12] => eflags[0x044,0x044]
327 cmpl imm8[12] r32.ud[34] => eflags[0x044,0x000]
328 cmpl imm8[34] r32.ud[12] => eflags[0x081,0x081]
329 cmpl imm8[12] r32.ud[34] => eflags[0x081,0x000]
334 cmpl imm8[3] m32.ud[2] => eflags[0x010,0x010]
335 cmpl imm8[2] m32.ud[3] => eflags[0x010,0x000]
336 cmpl imm8[12] m32.ud[12] => eflags[0x044,0x044]
337 cmpl imm8[12] m32.ud[34] => eflags[0x044,0x000]
338 cmpl imm8[34] m32.ud[12] => eflags[0x081,0x081]
339 cmpl imm8[12] m32.ud[34] => eflags[0x081,0x000]
344 cmpl imm32[3] eax.ud[2] => eflags[0x010,0x010]
345 cmpl imm32[2] eax.ud[3] => eflags[0x010,0x000]
346 cmpl imm32[12] eax.ud[12] => eflags[0x044,0x044]
347 cmpl imm32[12] eax.ud[34] => eflags[0x044,0x000]
348 cmpl imm32[34] eax.ud[12] => eflags[0x081,0x081]
349 cmpl imm32[12] eax.ud[34] => eflags[0x081,0x000]
354 cmpl imm32[3] r32.ud[2] => eflags[0x010,0x010]
355 cmpl imm32[2] r32.ud[3] => eflags[0x010,0x000]
356 cmpl imm32[12] r32.ud[12] => eflags[0x044,0x044]
357 cmpl imm32[12] r32.ud[34] => eflags[0x044,0x000]
358 cmpl imm32[34] r32.ud[12] => eflags[0x081,0x081]
359 cmpl imm32[12] r32.ud[34] => eflags[0x081,0x000]
364 cmpl imm32[3] m32.ud[2] => eflags[0x010,0x010]
365 cmpl imm32[2] m32.ud[3] => eflags[0x010,0x000]
366 cmpl imm32[12] m32.ud[12] => eflags[0x044,0x044]
367 cmpl imm32[12] m32.ud[34] => eflags[0x044,0x000]
368 cmpl imm32[34] m32.ud[12] => eflags[0x081,0x081]
369 cmpl imm32[12] m32.ud[34] => eflags[0x081,0x000]
374 cmpl r32.ud[3] r32.ud[2] => eflags[0x010,0x010]
375 cmpl r32.ud[2] r32.ud[3] => eflags[0x010,0x000]
376 cmpl r32.ud[12] r32.ud[12] => eflags[0x044,0x044]
377 cmpl r32.ud[12] r32.ud[34] => eflags[0x044,0x000]
378 cmpl r32.ud[34] r32.ud[12] => eflags[0x081,0x081]
379 cmpl r32.ud[12] r32.ud[34] => eflags[0x081,0x000]
380 cmpl r32.ud[100] r32.sd[-2147483600] => eflags[0x800,0x800]
381 cmpl r32.ud[50] r32.sd[-50] => eflags[0x800,0x000]
384 cmpl r32.ud[3] m32.ud[2] => eflags[0x010,0x010]
385 cmpl r32.ud[2] m32.ud[3] => eflags[0x010,0x000]
386 cmpl r32.ud[12] m32.ud[12] => eflags[0x044,0x044]
387 cmpl r32.ud[12] m32.ud[34] => eflags[0x044,0x000]
388 cmpl r32.ud[34] m32.ud[12] => eflags[0x081,0x081]
389 cmpl r32.ud[12] m32.ud[34] => eflags[0x081,0x000]
390 cmpl r32.ud[100] m32.sd[-2147483600] => eflags[0x800,0x800]
391 cmpl r32.ud[50] m32.sd[-50] => eflags[0x800,0x000]
394 cmpl m32.ud[3] r32.ud[2] => eflags[0x010,0x010]
395 cmpl m32.ud[2] r32.ud[3] => eflags[0x010,0x000]
396 cmpl m32.ud[12] r32.ud[12] => eflags[0x044,0x044]
397 cmpl m32.ud[12] r32.ud[34] => eflags[0x044,0x000]
398 cmpl m32.ud[34] r32.ud[12] => eflags[0x081,0x081]
399 cmpl m32.ud[12] r32.ud[34] => eflags[0x081,0x000]
400 cmpl m32.ud[100] r32.sd[-2147483600] => eflags[0x800,0x800]
401 cmpl m32.ud[50] r32.sd[-50] => eflags[0x800,0x000]
412 cmpxchgl eflags[0x40,0x00] eax.ud[1234] : r32.ud[5678] r32.ud[1234] => eflags[0x40,0x40] eax.ud[1234] 0.ud[5678] 1.ud[5678]
413 cmpxchgl eflags[0x40,0x40] eax.ud[1234] : r32.ud[5678] r32.ud[3456] => eflags[0x40,0x00] eax.ud[3456] 0.ud[5678] 1.ud[3456]
414 cmpxchgl eflags[0x40,0x00] eax.ud[1234] : r32.ud[5678] m32.ud[1234] => eflags[0x40,0x40] eax.ud[1234] 0.ud[5678] 1.ud[5678]
415 cmpxchgl eflags[0x40,0x40] eax.ud[1234] : r32.ud[5678] m32.ud[3456] => eflags[0x40,0x00] eax.ud[3456] 0.ud[5678] 1.ud[3456]
427 decl r32.ud[12345678] => 0.ud[12345677]
428 decl m32.ud[12345678] => 0.ud[12345677]
433 divl edx.ud[251958] eax.ud[673192206] : r32.ud[87654321] => eax.ud[12345678] edx.ud[20783136]
434 divl edx.ud[251958] eax.ud[673192206] : m32.ud[87654321] => eax.ud[12345678] edx.ud[20783136]
455 imull imm8[123] r32.ud[67890] => 1.ud[8350470]
456 imull imm8[123] r32.ud[67890] r32.ud[0] => 2.ud[8350470]
457 imull imm8[123] m32.ud[67890] r32.ud[0] => 2.ud[8350470]
458 imull imm32[12345] r32.ud[67890] => 1.ud[838102050]
459 imull imm32[12345] r32.ud[67890] r32.ud[0] => 2.ud[838102050]
460 imull imm32[12345] m32.ud[67890] r32.ud[0] => 2.ud[838102050]
461 imull r32.ud[12345] r32.ud[67890] => 1.ud[838102050]
462 imull m32.ud[12345] r32.ud[67890] => 1.ud[838102050]
467 incl r32.ud[12345678] => 0.ud[12345679]
468 incl m32.ud[12345678] => 0.ud[12345679]
481 movl imm32[12345678] r32.ud[0] => 1.ud[12345678]
482 movl imm32[12345678] m32.ud[0] => 1.ud[12345678]
483 movl r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
484 movl r32.ud[12345678] m32.ud[0] => 1.ud[12345678]
485 movl m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
494 movzbl r8.ub[123] r32.ud[0] => 1.ud[123]
495 movzbl m8.ub[246] r32.ud[0] => 1.ud[246]
496 movzwl r16.uw[12345] r32.ud[0] => 1.ud[12345]
497 movzwl m16.uw[49380] r32.ud[0] => 1.ud[49380]
502 mull eax.ud[12345678] : r32.ud[12345678] => edx.ud[35487] eax.ud[260846532]
503 mull eax.ud[12345678] : m32.ud[12345678] => edx.ud[35487] eax.ud[260846532]
514 notl r32.ud[0xff00f0ca] => 0.ud[0x00ff0f35]
515 notl m32.ud[0xff00f0ca] => 0.ud[0x00ff0f35]
529 orl imm8[0x31] r32.ud[0x12345678] => 1.ud[0x12345679]
530 orl imm32[0x86427531] eax.ud[0x12345678] => 1.ud[0x96767779]
531 orl imm32[0x86427531] ebx.ud[0x12345678] => 1.ud[0x96767779]
532 orl imm32[0x86427531] m32.ud[0x12345678] => 1.ud[0x96767779]
533 orl r32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x96767779]
534 orl r32.ud[0x86427531] m32.ud[0x12345678] => 1.ud[0x96767779]
535 orl m32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x96767779]
548 rcll eflags[0x1,0x0] : r32.ud[0xff00f0ca] => 0.ud[0xfe01e194] eflags[0x1,0x1]
549 rcll eflags[0x1,0x0] : m32.ud[0xff00f0ca] => 0.ud[0xfe01e194] eflags[0x1,0x1]
550 rcll eflags[0x1,0x0] : imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1]
551 rcll eflags[0x1,0x0] : imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1]
552 rcll eflags[0x1,0x0] : cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1]
553 rcll eflags[0x1,0x0] : cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1]
566 rcrl eflags[0x1,0x1] : r32.ud[0xff00f0ca] => 0.ud[0xff807865] eflags[0x1,0x0]
567 rcrl eflags[0x1,0x1] : m32.ud[0xff00f0ca] => 0.ud[0xff807865] eflags[0x1,0x0]
568 rcrl eflags[0x1,0x0] : imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1]
569 rcrl eflags[0x1,0x0] : imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1]
570 rcrl eflags[0x1,0x0] : cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1]
571 rcrl eflags[0x1,0x0] : cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1]
584 roll r32.ud[0xff00f0ca] => 0.ud[0xfe01e195]
585 roll m32.ud[0xff00f0ca] => 0.ud[0xfe01e195]
586 roll imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0caff]
587 roll imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0caff]
588 roll cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0caff]
589 roll cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0caff]
602 rorl r32.ud[0xff00f0ca] => 0.ud[0x7f807865]
603 rorl m32.ud[0xff00f0ca] => 0.ud[0x7f807865]
604 rorl imm8[8] r32.ud[0xff00f0ca] => 1.ud[0xcaff00f0]
605 rorl imm8[8] m32.ud[0xff00f0ca] => 1.ud[0xcaff00f0]
606 rorl cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0xcaff00f0]
607 rorl cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0xcaff00f0]
622 sall r32.ud[0xff00f0ca] => 0.ud[0xfe01e194]
623 sall m32.ud[0xff00f0ca] => 0.ud[0xfe01e194]
624 sall imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca00]
625 sall imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca00]
626 sall cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca00]
627 sall cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca00]
640 sarl r32.ud[0xff00f0ca] => 0.ud[0xff807865]
641 sarl m32.ud[0xff00f0ca] => 0.ud[0xff807865]
642 sarl imm8[8] r32.ud[0xff00f0ca] => 1.ud[0xffff00f0]
643 sarl imm8[8] m32.ud[0xff00f0ca] => 1.ud[0xffff00f0]
644 sarl cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0xffff00f0]
645 sarl cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0xffff00f0]
672 sbbl eflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654309]
673 sbbl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654308]
674 sbbl eflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[75308643]
675 sbbl eflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[75308642]
676 sbbl eflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308643]
677 sbbl eflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308642]
678 sbbl eflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[75308643]
679 sbbl eflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[75308642]
680 sbbl eflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[75308643]
681 sbbl eflags[0x1,0x1] : r32.ud[12345678] r32.ud[87654321] => 1.ud[75308642]
682 sbbl eflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[75308643]
683 sbbl eflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[75308642]
684 sbbl eflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[75308643]
685 sbbl eflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[75308642]
890 shll r32.ud[0xff00f0ca] => 0.ud[0xfe01e194]
891 shll m32.ud[0xff00f0ca] => 0.ud[0xfe01e194]
892 shll imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca00]
893 shll imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca00]
894 shll cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca00]
895 shll cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca00]
908 shrl r32.ud[0xff00f0ca] => 0.ud[0x7f807865]
909 shrl m32.ud[0xff00f0ca] => 0.ud[0x7f807865]
910 shrl imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00ff00f0]
911 shrl imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00ff00f0]
912 shrl cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00ff00f0]
913 shrl cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00ff00f0]
922 shldl imm8[1] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0xfe01e195]
923 shldl imm8[1] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0xfe01e195]
924 shldl imm8[8] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0x00f0caff]
925 shldl imm8[8] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0x00f0caff]
926 shldl cl.ub[1] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0xfe01e195]
927 shldl cl.ub[1] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0xfe01e195]
928 shldl cl.ub[8] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0x00f0caff]
929 shldl cl.ub[8] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0x00f0caff]
938 shrdl imm8[1] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0x7f807865]
939 shrdl imm8[1] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0x7f807865]
940 shrdl imm8[8] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0xcaff00f0]
941 shrdl imm8[8] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0xcaff00f0]
942 shrdl cl.ub[1] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0x7f807865]
943 shrdl cl.ub[1] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0x7f807865]
944 shrdl cl.ub[8] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0xcaff00f0]
945 shrdl cl.ub[8] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0xcaff00f0]
963 subl imm8[12] r32.ud[87654321] => 1.ud[87654309]
964 subl imm32[12345678] r32.ud[87654321] => 1.ud[75308643]
965 subl imm32[12345678] eax.ud[87654321] => 1.ud[75308643]
966 subl imm32[12345678] ebx.ud[87654321] => 1.ud[75308643]
967 subl r32.ud[12345678] r32.ud[87654321] => 1.ud[75308643]
968 subl r32.ud[12345678] m32.ud[87654321] => 1.ud[75308643]
969 subl m32.ud[12345678] r32.ud[87654321] => 1.ud[75308643]
1020 testl imm32[0x1a1a1a1a] eax.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
1021 testl imm32[0x5a5a5a5a] eax.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
1022 testl imm32[0x1a1a1a1a] eax.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
1023 testl imm32[0xa1a1a1a1] eax.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
1024 testl imm32[0xa5a5a5a5] eax.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
1025 testl imm32[0x1a1a1a1a] ebx.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
1026 testl imm32[0x5a5a5a5a] ebx.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
1027 testl imm32[0x1a1a1a1a] ebx.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
1028 testl imm32[0xa1a1a1a1] ebx.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
1029 testl imm32[0xa5a5a5a5] ebx.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
1030 testl imm32[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
1031 testl imm32[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
1032 testl imm32[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
1033 testl imm32[0xa1a1a1a1] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
1034 testl imm32[0xa5a5a5a5] m32.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
1035 testl r32.ud[0x1a1a1a1a] r32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
1036 testl r32.ud[0x5a5a5a5a] r32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
1037 testl r32.ud[0x1a1a1a1a] r32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
1038 testl r32.ud[0xa1a1a1a1] r32.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
1039 testl r32.ud[0xa5a5a5a5] r32.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
1040 testl r32.ud[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
1041 testl r32.ud[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
1042 testl r32.ud[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
1043 testl r32.ud[0xa1a1a1a1] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
1044 testl r32.ud[0xa5a5a5a5] m32.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
1049 ###xaddl r32.ud[12345678] r32.ud[87654321] => 0.ud[87654321] 1.ud[99999999]
1050 xaddl r32.ud[12345678] m32.ud[87654321] => 0.ud[87654321] 1.ud[99999999]
1059 xchgl eax.ud[12345678] ebx.ud[87654321] => 0.ud[87654321] 1.ud[12345678]
1060 xchgl ebx.ud[12345678] eax.ud[87654321] => 0.ud[87654321] 1.ud[12345678]
1061 xchgl ebx.ud[12345678] ecx.ud[87654321] => 0.ud[87654321] 1.ud[12345678]
1062 xchgl r32.ud[12345678] m32.ud[87654321] => 0.ud[87654321] 1.ud[12345678]
1063 xchgl m32.ud[12345678] r32.ud[87654321] => 0.ud[87654321] 1.ud[12345678]
1077 xorl imm8[0x31] r32.ud[0x12345678] => 1.ud[0x12345649]
1078 xorl imm32[0x86427531] eax.ud[0x12345678] => 1.ud[0x94762349]
1079 xorl imm32[0x86427531] ebx.ud[0x12345678] => 1.ud[0x94762349]
1080 xorl imm32[0x86427531] m32.ud[0x12345678] => 1.ud[0x94762349]
1081 xorl r32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x94762349]
1082 xorl r32.ud[0x86427531] m32.ud[0x12345678] => 1.ud[0x94762349]
1083 xorl m32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x94762349]
