Lines Matching refs:LSL
125 ADD Counter, Temp, Counter, LSL #8 ;// [0 0 H W]
136 SUB pSrc, pSrc, srcStep, LSL #2
145 RSB ValCD0, ValEB0, ValCD0, LSL #2 ;// 4*(Off+C+D) - (Off+B+E)
147 LDR ValD, [pSrc, srcStep, LSL #1] ;// Load [d3 d2 d1 d0]
149 RSB ValCD1, ValEB1, ValCD1, LSL #2
153 LDR ValF, [pSrc, srcStep, LSL #2] ;// Load [f3 f2 f1 f0]
155 ADD ValCD0, ValCD0, ValCD0, LSL #2 ;// 5 * [4*(Off+C+D) - (Off+B+E)]
156 ADD ValCD1, ValCD1, ValCD1, LSL #2
159 RSB ValED1, ValCF1, ValED1, LSL #2
161 SUB ValA, pSrc, srcStep, LSL #1
163 RSB ValED0, ValCF0, ValED0, LSL #2 ;// 4*(Off+E+D) - (Off+C+F)
164 ADD ValED1, ValED1, ValED1, LSL #2
165 ADD ValED0, ValED0, ValED0, LSL #2 ;// 5 * [4*(Off+E+D) - (Off+C+F)]
172 LDR ValG, [pSrc, srcStep, LSL #2] ;// Load [g3 g2 g1 g0]
187 ADD pSrc, pSrc, srcStep, LSL #1
261 ORR Acc0, Acc0, Acc1, LSL #8
262 ORR Acc2, Acc2, Acc3, LSL #8
264 ORR Acc0, Acc0, Acc2, LSL #16
268 SUB pDst, pDst, dstStep, LSL #2
269 SUB pSrc, pSrc, srcStep, LSL #2
