Lines Matching full:pipeline
7136 that otherwise would cause pipeline stalls. This pass is
23135 `dbra'-like instruction and avoids pipeline stalls associated with the
23502 output is not available for multiple cycles (*note Processor pipeline
24048 * Processor pipeline description:: Specifying information for insn scheduling.
24555 File: gccint.info, Node: Delay Slots, Next: Processor pipeline description, Prev: Constant Attributes, Up: Insn Attributes
24624 File: gccint.info, Node: Processor pipeline description, Prev: Delay Slots, Up: Insn Attributes
24626 16.19.8 Specifying processor pipeline description
24634 Such "interlock (pipeline) delay" causes interruption of the fetching
24657 processor parallelism (or "pipeline description"). GCC machine
24662 The GCC instruction scheduler uses a "pipeline hazard recognizer" to
24664 a given simulated processor cycle. The pipeline hazard recognizer is
24665 automatically generated from the processor pipeline description. The
24666 pipeline hazard recognizer generated from the machine description is
24673 automaton-based processor pipeline description. The order of these
24677 generated and used for the pipeline hazards recognition. Sometimes the
24678 generated finite state automaton used by the pipeline hazard recognizer
24729 The following construction is the major one to describe pipeline
24737 automaton based pipeline description. The latency time is used for all
24739 pipeline description, the given latency time is only used for true
24757 defined. Such cases are not checked during generation of the pipeline
24760 contain `symbol_ref'). It is also not checked during the pipeline
24810 In such case, you can simplify the pipeline description by describing
24924 You can control the generator of the pipeline hazard recognizer with
24959 generated states, you could interrupt the generator of the pipeline
24971 All simple integer insns can be executed in any integer pipeline and
24973 issued into the first pipeline unless it is reserved, otherwise they
24974 are issued into the second pipeline. Integer division and
24976 pipeline and their results are ready correspondingly in 8 and 4 cycles.
31564 using the traditional pipeline description that an output- or
31566 If the scheduler using the automaton based pipeline description,
31571 *note Processor pipeline description::.
31656 pipeline hazard recognizer is changed as if the insn were scheduled
31658 may simplify the automaton pipeline description for some VLIW
31660 automaton based pipeline description. The default is not to
31706 pipeline B. The processor may issue the 1st insn into A and the
31712 pipeline hazard recognizer. We try quickly and easy many insn
43810 * absence_set: Processor pipeline description.
43976 * automata_option: Processor pipeline description.
43978 * automaton based pipeline description: Processor pipeline description.
43980 * automaton based scheduler: Processor pipeline description.
44364 * data bypass: Processor pipeline description.
44366 * data dependence delays: Processor pipeline description.
44484 * define_automaton: Processor pipeline description.
44486 * define_bypass: Processor pipeline description.
44497 * define_cpu_unit: Processor pipeline description.
44511 * define_insn_reservation: Processor pipeline description.
44521 * define_query_cpu_unit: Processor pipeline description.
44524 * define_reservation: Processor pipeline description.
44548 * deterministic finite state automaton: Processor pipeline description.
44663 * exclusion_set: Processor pipeline description.
44705 * final_absence_set: Processor pipeline description.
44708 * final_presence_set: Processor pipeline description.
44715 * finite state automaton minimization: Processor pipeline description.
45490 * instruction latency time: Processor pipeline description.
45513 * interlock delays: Processor pipeline description.
45905 * nondeterministic finite state automaton: Processor pipeline description.
46054 * pipeline hazard recognizer: Processor pipeline description.
46112 * presence_set: Processor pipeline description.
46122 * processor functional units: Processor pipeline description.
46124 * processor pipeline description: Processor pipeline description.
46163 * querying function unit reservations: Processor pipeline description.
46294 * regular expressions: Processor pipeline description.
46307 * reservation delays: Processor pipeline description.
46343 * RISC: Processor pipeline description.
47452 * VLIW: Processor pipeline description.
47759 Node: Processor pipeline description1039899
47760 Ref: Processor pipeline description-Footnote-11057517
