| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 122 // DstReg = LDriw_pred [R30], ofst.
123 int DstReg = MI->getOperand(0).getReg();
124 assert(Hexagon::PredRegsRegClass.contains(DstReg) &&
145 DstReg).addReg(HEXAGON_RESERVED_REG_2);
154 DstReg).addReg(HEXAGON_RESERVED_REG_2);
160 DstReg).addReg(HEXAGON_RESERVED_REG_2);
|
| HexagonPeephole.cpp | 133 unsigned DstReg = Dst.getReg();
136 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
141 PeepholeMap[DstReg] = SrcReg;
157 unsigned DstReg = Dst.getReg();
159 PeepholeDoubleRegsMap[DstReg] =
169 unsigned DstReg = Dst.getReg();
172 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
177 PeepholeMap[DstReg] = SrcReg;
192 unsigned DstReg = Dst.getReg();
194 if (TargetRegisterInfo::isVirtualRegister(DstReg) &
[all...] |
| /external/llvm/lib/CodeGen/ |
| ExpandPostRAPseudos.cpp | 52 void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
64 /// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead,
68 ExpandPostRA::TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
72 if (MII->addRegisterDead(DstReg, TRI))
102 unsigned DstReg = MI->getOperand(0).getReg();
108 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
110 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
122 if (DstReg != InsReg) {
134 // Implicitly define DstReg for subsequent uses.
137 CopyMI->addRegisterDefined(DstReg);
[all...] |
| OptimizePHIs.cpp | 87 unsigned DstReg = MI->getOperand(0).getReg();
100 if (SrcReg == DstReg)
130 unsigned DstReg = MI->getOperand(0).getReg();
131 assert(TargetRegisterInfo::isVirtualRegister(DstReg) &&
142 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DstReg),
|
| RegisterCoalescer.h | 31 /// DstReg - The register that will be left after coalescing. It can be a
33 unsigned DstReg;
35 /// SrcReg - the virtual register that will be coalesced into dstReg.
38 /// DstIdx - The sub-register index of the old DstReg in the new coalesced
52 /// Flipped - True when DstReg and SrcReg are reversed from the original
56 /// NewRC - The register class of the coalesced register, or NULL if DstReg
58 /// SrcReg and DstReg.
63 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0),
70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
77 /// flip - Swap SrcReg and DstReg. Return false if swapping is impossibl
[all...] |
| MachineSink.cpp | 130 unsigned DstReg = MI->getOperand(0).getReg();
132 !TargetRegisterInfo::isVirtualRegister(DstReg) ||
137 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg);
146 MRI->replaceRegWith(DstReg, SrcReg);
|
| PeepholeOptimizer.cpp | 144 unsigned SrcReg, DstReg, SubIdx;
145 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
148 if (TargetRegisterInfo::isPhysicalRegister(DstReg) ||
156 // Ensure DstReg can get a register class that actually supports
158 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
175 UI = MRI->use_nodbg_begin(DstReg), UE = MRI->use_nodbg_end();
258 UI = MRI->use_nodbg_begin(DstReg), UE = MRI->use_nodbg_end();
271 // About to add uses of DstReg, clear DstReg's kill flags.
273 MRI->clearKillFlags(DstReg);
[all...] |
| EarlyIfConversion.cpp | 112 // Latencies from Cond+Branch, TReg, and FReg to DstReg.
463 unsigned DstReg = PI.PHI->getOperand(0).getReg();
464 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg);
484 unsigned DstReg = MRI->createVirtualRegister(MRI->getRegClass(PHIDst));
485 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg);
488 // Rewrite PHI operands TPred -> (DstReg, Head), remove FPred.
493 PI.PHI->getOperand(i-2).setReg(DstReg);
|
| LiveDebugVariables.cpp | 566 unsigned DstReg = MI->getOperand(0).getReg();
572 if (!TargetRegisterInfo::isVirtualRegister(DstReg))
582 if (!LIS.hasInterval(DstReg))
584 LiveInterval *DstLI = &LIS.getInterval(DstReg);
[all...] |
| TwoAddressInstructionPass.cpp | 134 void ScanUses(unsigned DstReg, MachineBasicBlock *MBB,
145 void CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs, unsigned DstReg);
333 unsigned &SrcReg, unsigned &DstReg,
336 DstReg = 0;
338 DstReg = MI.getOperand(0).getReg();
341 DstReg = MI.getOperand(0).getReg();
347 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
382 unsigned SrcReg, DstReg;
385 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
393 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.cpp | 208 unsigned DstReg = MI.getOperand(0).getReg();
210 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
211 .addReg(DstReg).addImm(-Offset);
213 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
214 .addReg(DstReg).addImm(Offset);
|
| MSP430ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 209 unsigned DstReg = MI->getOperand(0).getReg();
235 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead));
|
| Thumb2ITBlockPass.cpp | 117 unsigned DstReg = MI->getOperand(0).getReg();
121 if (Uses.count(DstReg) || Defs.count(SrcReg))
|
| ARMExpandPseudoInsts.cpp | 388 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
390 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
428 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
516 unsigned DstReg = 0;
520 DstReg = MI.getOperand(OpIdx++).getReg();
521 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
570 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
617 unsigned DstReg = MI.getOperand(0).getReg();
626 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
628 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)
[all...] |
| ARMAsmPrinter.cpp | [all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| ARMFastISel.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 328 unsigned DstReg = I->getOperand(0).getReg();
338 BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(SubReg);
343 unsigned DstReg = I->getOperand(0).getReg();
351 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpeven))
353 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpodd))
|
| MipsISelDAGToDAG.cpp | 225 unsigned DstReg = 0, ZeroReg = 0;
231 DstReg = MI.getOperand(0).getReg();
236 DstReg = MI.getOperand(0).getReg();
240 if (!DstReg)
244 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
|
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 132 unsigned DstReg = MI->getOperand(0).getReg();
135 if (DstReg != SrcReg)
136 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
140 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
144 if (DstReg != SrcReg)
145 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
149 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
153 if (DstReg != SrcReg)
154 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
158 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 800 unsigned DstReg = VA.getLocReg();
803 if (!SrcRC->contains(DstReg))
806 DstReg).addReg(SrcReg);
[all...] |
| X86InstrInfo.cpp | [all...] |
